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<html><head><title>8051 for EE301</title></head>
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<h2>Important Files</h2>
To create a peripheral that works with 8051 model, it should fit
into the current 8051 model.
<p>
<a href="javascript:if(confirm('http://www.ee.umr.edu/~mrmayer/8051/top_level.gif \n\nThis file was not retrieved by Teleport Pro, because the server reports that this file cannot be found. \n\nDo you want to open it from the server?'))window.location='http://www.ee.umr.edu/%7Emrmayer/8051/top_level.gif'" tppabs="http://www.ee.umr.edu/%7Emrmayer/8051/top_level.gif">Graphical View</a> of Architecture<br>
<a href="javascript:if(confirm('http://www.ee.umr.edu/~mrmayer/8051/struct/mc8051_struct.vhdl \n\nThis file was not retrieved by Teleport Pro, because the server reports that this file cannot be found. \n\nDo you want to open it from the server?'))window.location='http://www.ee.umr.edu/%7Emrmayer/8051/struct/mc8051_struct.vhdl'" tppabs="http://www.ee.umr.edu/%7Emrmayer/8051/struct/mc8051_struct.vhdl">VHDL Text</a> of Entity / Architecture Pair<br>
<a href="index-3.htm" tppabs="http://www.ee.umr.edu/%7Emrmayer/8051/struct/">VHDL examples</a> of other registers e.g. acc <br>
<p>
<h2>SPECIFICATION FOR 8051 PERIPHERALS</h2>
Each peripheral is memory mapped to a location or locations somewhere
between 16#80# and 16#FF#. For instance, a UART has control buffer at
location 16#98# and data buffer at 16#99#. The peripheral should watch for
these addresses on the global bus, and then respond by writing / reading to
/ from the data global bus. Since the 8051 has both direct and indirect
memory addressing modes, it is important to know which is being used. The
special function registers are all accessed through DIRECT addressing.
<p>
After reading / writing to the global bus, the port raises the acknowledge
signal, ACKNOW. When the rd_gb or wr_gb is reset (by the global bus controller)
then the ACKNOW is brought low.
<p>
The entity for the peripheral should have port IO for the following signals
so that it can communicate to the CPU:
<p>
<pre>
-- the addr global bus, watch for relevant addresses
addr_gb : IN UNSIGNED(7 DOWNTO 0);
-- '1' on indirect_sel means indirect addressing is being used.
-- In this case, the peripheral should NOT respond.
indirect_sel : IN std_logic;
-- the data global bus
data_gb : INOUT UNSIGNED(7 DOWNTO 0);
-- rd_gb - the cpu is trying to read from the peripheral
-- so drive the necessary data to data_gb
rd_gb : IN std_logic;
-- wr_gb - the cpu is trying to write to the peripheral
-- so read the necessary data from data_gb
wr_gb : IN std_logic;
-- the peripheral raises acknow when it is finished with
-- the read / write and lowers it when the rd_gb or wr_gb
-- goes back low.
acknow : OUT std_logic;
</pre>
<p>
Additionally, other IO may need to be used (since it is a peripheral). For
instance, to tap into port 3 bit 0, two signals are used. One to tell the
pin to use a "special function" (as opposed to just the latch) and another
to carry the desired signal. The select line should be low whenever the pin
is not being used (so that the latch will drive it) but set high whenever
the peripheral needs to use the pin for input or output.
<p>
<pre>
port3_0_sel : OUT std_logic; -- '1' selects special function
serial_txrx : INOUT std_logic; -- data for port 3_0
</pre>
<p>
Here are some quick timing specs for the peripherals.
<p>
<pre>
FOR A CPU WRITE
addr_gb XXXX|ADDR |XXX -- addr and data are driven w/ clock
data_gb XXXX|DATA |XXXXX
___
wr_gb ______| |_____ -- wr_gb is set shortly after clock
peripheral responds to rising edge by raising acknow, this
causes the bus controller to lower wr_gb and acknow then falls.
___
acknow _______| |____
FOR A CPU READ
addr_gb XXXX|ADDR |XXXX -- addr is driven w/ clk
_____
rd_gb ______| |_____ -- rd_gb is set shortly after clk
peripheral responds to rising edge by setting data_gb and acknow
this causes the bus controller to lower rd_gb and acknow then falls
data_gb XXXXXXXX|DATA |XXX
_____
acknow ________| |____
Note: For all practical purposes, treat indirect_sel as another address.
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