cpu_pack.vhd

this is a file about vhdl source code realtinf 8051 through 8051

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

PACKAGE cpu_pack IS
    CONSTANT nothing     : std_logic_vector(3 DOWNTO 0) := "0000";
    CONSTANT zeros       : std_logic_vector(3 DOWNTO 0) := "0001";
--    CONSTANT pass_result : std_logic_vector(3 DOWNTO 0) := "0001";
    CONSTANT use_acc     : std_logic_vector(3 DOWNTO 0) := "0010";
    CONSTANT use_reg     : std_logic_vector(3 DOWNTO 0) := "0100";    
    CONSTANT immed       : std_logic_vector(3 DOWNTO 0) := "0101";    
    CONSTANT indirect_t	 : std_logic_vector(3 DOWNTO 0) := "1100";    
    CONSTANT direct_t    : std_logic_vector(3 DOWNTO 0) := "1101";    
    CONSTANT rd_at_sp    : std_logic_vector(3 DOWNTO 0) := "0011";    
    CONSTANT wr_at_sp    : std_logic_vector(3 DOWNTO 0) := "0011";    
    CONSTANT bit_addr    : std_logic_vector(3 DOWNTO 0) := "1110";
    CONSTANT same_as_t1  : std_logic_vector(3 DOWNTO 0) := "1000";
--    CONSTANT same_as_t2  : std_logic_vector(3 DOWNTO 0) := "1001";
--    CONSTANT pc_lo       : std_logic_vector(3 DOWNTO 0) := "0110";    
--    CONSTANT pc_hi       : std_logic_vector(3 DOWNTO 0) := "0111";    

-- CPU COMMANDS
    -- These first 4 commands all use the "standard" alu_data
    CONSTANT pass_tmp1     : std_logic_vector(3 DOWNTO 0) := "0000";    
    CONSTANT pass_tmp2     : std_logic_vector(3 DOWNTO 0) := "0001";    
    CONSTANT reserved1     : std_logic_vector(3 DOWNTO 0) := "0010";
    CONSTANT add_instr     : std_logic_vector(3 DOWNTO 0) := "0011";    
    -- A mask for these commands
    CONSTANT std_alu_data  : std_logic_vector(3 DOWNTO 0) := "00--";

    CONSTANT mul_instr     : std_logic_vector(3 DOWNTO 0) := "0100";
    CONSTANT div_instr     : std_logic_vector(3 DOWNTO 0) := "0101";
    CONSTANT da_instr      : std_logic_vector(3 DOWNTO 0) := "0110";
    CONSTANT reserved2     : std_logic_vector(3 DOWNTO 0) := "0111";

    -- these 4 commands use different alu_data
    CONSTANT rotate        : std_logic_vector(3 DOWNTO 0) := "1000";    
    CONSTANT logic         : std_logic_vector(3 DOWNTO 0) := "1001";    
    CONSTANT compare_1_2   : std_logic_vector(3 DOWNTO 0) := "1010";    
    CONSTANT xchd1         : std_logic_vector(3 DOWNTO 0) := "1011";

    -- These bit commands all use logic alu_data
    CONSTANT clr_bit       : std_logic_vector(3 DOWNTO 0) := "1100";    
    CONSTANT set_bit       : std_logic_vector(3 DOWNTO 0) := "1101";    
    CONSTANT bit_logic     : std_logic_vector(3 DOWNTO 0) := "1110";    
    CONSTANT cpl_bit_logic : std_logic_vector(3 DOWNTO 0) := "1111";    

    -- standard alu data for pre-processing to temp1
    CONSTANT t1_cpl        : std_logic_vector(2 DOWNTO 0) := "100";
    CONSTANT t1_cpl_val    : std_logic_vector(2 DOWNTO 0) := "1--";
    CONSTANT t1_inc        : std_logic_vector(2 DOWNTO 0) := "001";
    CONSTANT t1_inc_val    : std_logic_vector(2 DOWNTO 0) := "--1";
    CONSTANT t1_dec        : std_logic_vector(2 DOWNTO 0) := "010";
    CONSTANT t1_dec_val    : std_logic_vector(2 DOWNTO 0) := "-1-";

    -- ROTATE
    CONSTANT rr_instr      : std_logic_vector(2 DOWNTO 0) := "000";
    CONSTANT rrc_instr     : std_logic_vector(2 DOWNTO 0) := "001";
    CONSTANT rl_instr      : std_logic_vector(2 DOWNTO 0) := "010";
    CONSTANT rlc_instr     : std_logic_vector(2 DOWNTO 0) := "011";
    CONSTANT swap_instr    : std_logic_vector(2 DOWNTO 0) := "100";
    CONSTANT xchd2         : std_logic_vector(2 DOWNTO 0) := "101";

    -- LOGIC / BIT LOGIC / CPL BIT LOGIC
    -- THESE CANNNOT BE CHANGED EASLIY!
    CONSTANT anl_instr     : std_logic_vector(2 DOWNTO 0) := "101";
    CONSTANT orl_instr     : std_logic_vector(2 DOWNTO 0) := "100";
    CONSTANT xrl_instr     : std_logic_vector(2 DOWNTO 0) := "110";
    CONSTANT mov_instr     : std_logic_vector(2 DOWNTO 0) := "100";
    -- ONLY for LOGIC, not bit logic
    CONSTANT cpl_instr     : std_logic_vector(2 DOWNTO 0) := "011";


END PACKAGE cpu_pack;