dip_pb_counter.tan.rpt

本程序有效的防止了按键的抖动

+---------------+-------------+-----------+-----------+-----------------+----------+
; N/A           ; None        ; -3.872 ns ; DipSwitch ; DipSwitch_flop1 ; clk      ;
; N/A           ; None        ; -4.119 ns ; PBSwitch  ; PBSwitch_flop1  ; clk      ;
+---------------+-------------+-----------+-----------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue May 19 16:20:03 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DIP_PB_Counter -c DIP_PB_Counter --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 167.48 MHz between source register "count[12]" and destination register "count[15]" (period= 5.971 ns)
    Info: + Longest register to register delay is 5.710 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y5_N1; Fanout = 3; REG Node = 'count[12]'
        Info: 2: + IC(1.269 ns) + CELL(0.442 ns) = 1.711 ns; Loc. = LC_X14_Y4_N9; Fanout = 1; COMB Node = 'Equal0~135'
        Info: 3: + IC(1.512 ns) + CELL(0.114 ns) = 3.337 ns; Loc. = LC_X12_Y5_N0; Fanout = 2; COMB Node = 'Equal0~139'
        Info: 4: + IC(0.424 ns) + CELL(0.114 ns) = 3.875 ns; Loc. = LC_X12_Y5_N4; Fanout = 16; COMB Node = 'Add0~1376'
        Info: 5: + IC(1.526 ns) + CELL(0.309 ns) = 5.710 ns; Loc. = LC_X14_Y4_N8; Fanout = 2; REG Node = 'count[15]'
        Info: Total cell delay = 0.979 ns ( 17.15 % )
        Info: Total interconnect delay = 4.731 ns ( 82.85 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.902 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
            Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X14_Y4_N8; Fanout = 2; REG Node = 'count[15]'
            Info: Total cell delay = 2.180 ns ( 75.12 % )
            Info: Total interconnect delay = 0.722 ns ( 24.88 % )
        Info: - Longest clock path from clock "clk" to source register is 2.902 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
            Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X13_Y5_N1; Fanout = 3; REG Node = 'count[12]'
            Info: Total cell delay = 2.180 ns ( 75.12 % )
            Info: Total interconnect delay = 0.722 ns ( 24.88 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "PBSwitch_flop1" (data pin = "PBSwitch", clock pin = "clk") is 4.171 ns
    Info: + Longest pin to register delay is 7.036 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_84; Fanout = 1; PIN Node = 'PBSwitch'
        Info: 2: + IC(5.083 ns) + CELL(0.478 ns) = 7.036 ns; Loc. = LC_X13_Y4_N2; Fanout = 4; REG Node = 'PBSwitch_flop1'
        Info: Total cell delay = 1.953 ns ( 27.76 % )
        Info: Total interconnect delay = 5.083 ns ( 72.24 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.902 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
        Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X13_Y4_N2; Fanout = 4; REG Node = 'PBSwitch_flop1'
        Info: Total cell delay = 2.180 ns ( 75.12 % )
        Info: Total interconnect delay = 0.722 ns ( 24.88 % )
Info: tco from clock "clk" to destination pin "Led_inv[3]" through register "Led[3]" is 8.313 ns
    Info: + Longest clock path from clock "clk" to source register is 2.902 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
        Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X11_Y5_N2; Fanout = 2; REG Node = 'Led[3]'
        Info: Total cell delay = 2.180 ns ( 75.12 % )
        Info: Total interconnect delay = 0.722 ns ( 24.88 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.187 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y5_N2; Fanout = 2; REG Node = 'Led[3]'
        Info: 2: + IC(3.079 ns) + CELL(2.108 ns) = 5.187 ns; Loc. = PIN_224; Fanout = 0; PIN Node = 'Led_inv[3]'
        Info: Total cell delay = 2.108 ns ( 40.64 % )
        Info: Total interconnect delay = 3.079 ns ( 59.36 % )
Info: th for register "DipSwitch_flop1" (data pin = "DipSwitch", clock pin = "clk") is -3.872 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X12_Y17_N2; Fanout = 1; REG Node = 'DipSwitch_flop1'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.841 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_219; Fanout = 1; PIN Node = 'DipSwitch'
        Info: 2: + IC(5.057 ns) + CELL(0.309 ns) = 6.841 ns; Loc. = LC_X12_Y17_N2; Fanout = 1; REG Node = 'DipSwitch_flop1'
        Info: Total cell delay = 1.784 ns ( 26.08 % )
        Info: Total interconnect delay = 5.057 ns ( 73.92 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 112 megabytes of memory during processing
    Info: Processing ended: Tue May 19 16:20:04 2009
    Info: Elapsed time: 00:00:01