dip_pb_counter.tan.qmsg

本程序有效的防止了按键的抖动

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[12\] register count\[15\] 167.48 MHz 5.971 ns Internal " "Info: Clock \"clk\" has Internal fmax of 167.48 MHz between source register \"count\[12\]\" and destination register \"count\[15\]\" (period= 5.971 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.710 ns + Longest register register " "Info: + Longest register to register delay is 5.710 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[12\] 1 REG LC_X13_Y5_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y5_N1; Fanout = 3; REG Node = 'count\[12\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[12] } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.269 ns) + CELL(0.442 ns) 1.711 ns Equal0~135 2 COMB LC_X14_Y4_N9 1 " "Info: 2: + IC(1.269 ns) + CELL(0.442 ns) = 1.711 ns; Loc. = LC_X14_Y4_N9; Fanout = 1; COMB Node = 'Equal0~135'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.711 ns" { count[12] Equal0~135 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.512 ns) + CELL(0.114 ns) 3.337 ns Equal0~139 3 COMB LC_X12_Y5_N0 2 " "Info: 3: + IC(1.512 ns) + CELL(0.114 ns) = 3.337 ns; Loc. = LC_X12_Y5_N0; Fanout = 2; COMB Node = 'Equal0~139'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.626 ns" { Equal0~135 Equal0~139 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.424 ns) + CELL(0.114 ns) 3.875 ns Add0~1376 4 COMB LC_X12_Y5_N4 16 " "Info: 4: + IC(0.424 ns) + CELL(0.114 ns) = 3.875 ns; Loc. = LC_X12_Y5_N4; Fanout = 16; COMB Node = 'Add0~1376'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.538 ns" { Equal0~139 Add0~1376 } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.526 ns) + CELL(0.309 ns) 5.710 ns count\[15\] 5 REG LC_X14_Y4_N8 2 " "Info: 5: + IC(1.526 ns) + CELL(0.309 ns) = 5.710 ns; Loc. = LC_X14_Y4_N8; Fanout = 2; REG Node = 'count\[15\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.835 ns" { Add0~1376 count[15] } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.979 ns ( 17.15 % ) " "Info: Total cell delay = 0.979 ns ( 17.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.731 ns ( 82.85 % ) " "Info: Total interconnect delay = 4.731 ns ( 82.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.710 ns" { count[12] Equal0~135 Equal0~139 Add0~1376 count[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.710 ns" { count[12] {} Equal0~135 {} Equal0~139 {} Add0~1376 {} count[15] {} } { 0.000ns 1.269ns 1.512ns 0.424ns 1.526ns } { 0.000ns 0.442ns 0.114ns 0.114ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.902 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.711 ns) 2.902 ns count\[15\] 2 REG LC_X14_Y4_N8 2 " "Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X14_Y4_N8; Fanout = 2; REG Node = 'count\[15\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.433 ns" { clk count[15] } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.12 % ) " "Info: Total cell delay = 2.180 ns ( 75.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.722 ns ( 24.88 % ) " "Info: Total interconnect delay = 0.722 ns ( 24.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk count[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk {} clk~out0 {} count[15] {} } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.902 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.711 ns) 2.902 ns count\[12\] 2 REG LC_X13_Y5_N1 3 " "Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X13_Y5_N1; Fanout = 3; REG Node = 'count\[12\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.433 ns" { clk count[12] } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.12 % ) " "Info: Total cell delay = 2.180 ns ( 75.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.722 ns ( 24.88 % ) " "Info: Total interconnect delay = 0.722 ns ( 24.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk count[12] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk {} clk~out0 {} count[12] {} } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk count[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk {} clk~out0 {} count[15] {} } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk count[12] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk {} clk~out0 {} count[12] {} } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 82 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 82 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.710 ns" { count[12] Equal0~135 Equal0~139 Add0~1376 count[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.710 ns" { count[12] {} Equal0~135 {} Equal0~139 {} Add0~1376 {} count[15] {} } { 0.000ns 1.269ns 1.512ns 0.424ns 1.526ns } { 0.000ns 0.442ns 0.114ns 0.114ns 0.309ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk count[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk {} clk~out0 {} count[15] {} } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk count[12] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk {} clk~out0 {} count[12] {} } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "PBSwitch_flop1 PBSwitch clk 4.171 ns register " "Info: tsu for register \"PBSwitch_flop1\" (data pin = \"PBSwitch\", clock pin = \"clk\") is 4.171 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.036 ns + Longest pin register " "Info: + Longest pin to register delay is 7.036 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns PBSwitch 1 PIN PIN_84 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_84; Fanout = 1; PIN Node = 'PBSwitch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PBSwitch } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.083 ns) + CELL(0.478 ns) 7.036 ns PBSwitch_flop1 2 REG LC_X13_Y4_N2 4 " "Info: 2: + IC(5.083 ns) + CELL(0.478 ns) = 7.036 ns; Loc. = LC_X13_Y4_N2; Fanout = 4; REG Node = 'PBSwitch_flop1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.561 ns" { PBSwitch PBSwitch_flop1 } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.953 ns ( 27.76 % ) " "Info: Total cell delay = 1.953 ns ( 27.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.083 ns ( 72.24 % ) " "Info: Total interconnect delay = 5.083 ns ( 72.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.036 ns" { PBSwitch PBSwitch_flop1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.036 ns" { PBSwitch {} PBSwitch~out0 {} PBSwitch_flop1 {} } { 0.000ns 0.000ns 5.083ns } { 0.000ns 1.475ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 38 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.902 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.711 ns) 2.902 ns PBSwitch_flop1 2 REG LC_X13_Y4_N2 4 " "Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X13_Y4_N2; Fanout = 4; REG Node = 'PBSwitch_flop1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.433 ns" { clk PBSwitch_flop1 } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.12 % ) " "Info: Total cell delay = 2.180 ns ( 75.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.722 ns ( 24.88 % ) " "Info: Total interconnect delay = 0.722 ns ( 24.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk PBSwitch_flop1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk {} clk~out0 {} PBSwitch_flop1 {} } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.036 ns" { PBSwitch PBSwitch_flop1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.036 ns" { PBSwitch {} PBSwitch~out0 {} PBSwitch_flop1 {} } { 0.000ns 0.000ns 5.083ns } { 0.000ns 1.475ns 0.478ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk PBSwitch_flop1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk {} clk~out0 {} PBSwitch_flop1 {} } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Led_inv\[3\] Led\[3\] 8.313 ns register " "Info: tco from clock \"clk\" to destination pin \"Led_inv\[3\]\" through register \"Led\[3\]\" is 8.313 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.902 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.711 ns) 2.902 ns Led\[3\] 2 REG LC_X11_Y5_N2 2 " "Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X11_Y5_N2; Fanout = 2; REG Node = 'Led\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.433 ns" { clk Led[3] } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.12 % ) " "Info: Total cell delay = 2.180 ns ( 75.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.722 ns ( 24.88 % ) " "Info: Total interconnect delay = 0.722 ns ( 24.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk Led[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk {} clk~out0 {} Led[3] {} } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.187 ns + Longest register pin " "Info: + Longest register to pin delay is 5.187 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Led\[3\] 1 REG LC_X11_Y5_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y5_N2; Fanout = 2; REG Node = 'Led\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Led[3] } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.079 ns) + CELL(2.108 ns) 5.187 ns Led_inv\[3\] 2 PIN PIN_224 0 " "Info: 2: + IC(3.079 ns) + CELL(2.108 ns) = 5.187 ns; Loc. = PIN_224; Fanout = 0; PIN Node = 'Led_inv\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.187 ns" { Led[3] Led_inv[3] } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 40.64 % ) " "Info: Total cell delay = 2.108 ns ( 40.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.079 ns ( 59.36 % ) " "Info: Total interconnect delay = 3.079 ns ( 59.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.187 ns" { Led[3] Led_inv[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.187 ns" { Led[3] {} Led_inv[3] {} } { 0.000ns 3.079ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { clk Led[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.902 ns" { clk {} clk~out0 {} Led[3] {} } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.187 ns" { Led[3] Led_inv[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.187 ns" { Led[3] {} Led_inv[3] {} } { 0.000ns 3.079ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "DipSwitch_flop1 DipSwitch clk -3.872 ns register " "Info: th for register \"DipSwitch_flop1\" (data pin = \"DipSwitch\", clock pin = \"clk\") is -3.872 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns DipSwitch_flop1 2 REG LC_X12_Y17_N2 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X12_Y17_N2; Fanout = 1; REG Node = 'DipSwitch_flop1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk DipSwitch_flop1 } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk DipSwitch_flop1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} DipSwitch_flop1 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.841 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.841 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns DipSwitch 1 PIN PIN_219 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_219; Fanout = 1; PIN Node = 'DipSwitch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DipSwitch } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.057 ns) + CELL(0.309 ns) 6.841 ns DipSwitch_flop1 2 REG LC_X12_Y17_N2 1 " "Info: 2: + IC(5.057 ns) + CELL(0.309 ns) = 6.841 ns; Loc. = LC_X12_Y17_N2; Fanout = 1; REG Node = 'DipSwitch_flop1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.366 ns" { DipSwitch DipSwitch_flop1 } "NODE_NAME" } } { "DIP_PB_Counter.vhd" "" { Text "E:/专业/EDA/实验/DIP_PB_Counter/DIP_PB_Counter.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns ( 26.08 % ) " "Info: Total cell delay = 1.784 ns ( 26.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.057 ns ( 73.92 % ) " "Info: Total interconnect delay = 5.057 ns ( 73.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.841 ns" { DipSwitch DipSwitch_flop1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.841 ns" { DipSwitch {} DipSwitch~out0 {} DipSwitch_flop1 {} } { 0.000ns 0.000ns 5.057ns } { 0.000ns 1.475ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk DipSwitch_flop1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} DipSwitch_flop1 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.841 ns" { DipSwitch DipSwitch_flop1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.841 ns" { DipSwitch {} DipSwitch~out0 {} DipSwitch_flop1 {} } { 0.000ns 0.000ns 5.057ns } { 0.000ns 1.475ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}