led.tan.rpt

本程序有效的防止了按键的抖动

+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Mon May 11 21:25:12 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Led -c Led --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 178.06 MHz between source register "count[1]" and destination register "Led[3]" (period= 5.616 ns)
    Info: + Longest register to register delay is 5.355 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y6_N0; Fanout = 4; REG Node = 'count[1]'
        Info: 2: + IC(1.250 ns) + CELL(0.114 ns) = 1.364 ns; Loc. = LC_X23_Y5_N9; Fanout = 1; COMB Node = 'Equal0~138'
        Info: 3: + IC(1.227 ns) + CELL(0.292 ns) = 2.883 ns; Loc. = LC_X23_Y6_N6; Fanout = 2; COMB Node = 'Equal0~139'
        Info: 4: + IC(0.472 ns) + CELL(0.114 ns) = 3.469 ns; Loc. = LC_X23_Y6_N1; Fanout = 5; COMB Node = 'PB_valid~42'
        Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 3.765 ns; Loc. = LC_X23_Y6_N2; Fanout = 4; COMB Node = 'Led[0]~317'
        Info: 6: + IC(0.723 ns) + CELL(0.867 ns) = 5.355 ns; Loc. = LC_X22_Y6_N5; Fanout = 2; REG Node = 'Led[3]'
        Info: Total cell delay = 1.501 ns ( 28.03 % )
        Info: Total interconnect delay = 3.854 ns ( 71.97 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.909 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
            Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X22_Y6_N5; Fanout = 2; REG Node = 'Led[3]'
            Info: Total cell delay = 2.180 ns ( 74.94 % )
            Info: Total interconnect delay = 0.729 ns ( 25.06 % )
        Info: - Longest clock path from clock "clk" to source register is 2.909 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
            Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X24_Y6_N0; Fanout = 4; REG Node = 'count[1]'
            Info: Total cell delay = 2.180 ns ( 74.94 % )
            Info: Total interconnect delay = 0.729 ns ( 25.06 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "PBSwitch_flop1" (data pin = "PBSwitch", clock pin = "clk") is 6.028 ns
    Info: + Longest pin to register delay is 8.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_48; Fanout = 1; PIN Node = 'PBSwitch'
        Info: 2: + IC(7.122 ns) + CELL(0.309 ns) = 8.900 ns; Loc. = LC_X22_Y5_N2; Fanout = 4; REG Node = 'PBSwitch_flop1'
        Info: Total cell delay = 1.778 ns ( 19.98 % )
        Info: Total interconnect delay = 7.122 ns ( 80.02 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.909 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
        Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X22_Y5_N2; Fanout = 4; REG Node = 'PBSwitch_flop1'
        Info: Total cell delay = 2.180 ns ( 74.94 % )
        Info: Total interconnect delay = 0.729 ns ( 25.06 % )
Info: tco from clock "clk" to destination pin "Led_inv[1]" through register "Led[1]" is 8.963 ns
    Info: + Longest clock path from clock "clk" to source register is 2.909 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
        Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X23_Y6_N8; Fanout = 4; REG Node = 'Led[1]'
        Info: Total cell delay = 2.180 ns ( 74.94 % )
        Info: Total interconnect delay = 0.729 ns ( 25.06 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.830 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y6_N8; Fanout = 4; REG Node = 'Led[1]'
        Info: 2: + IC(3.706 ns) + CELL(2.124 ns) = 5.830 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'Led_inv[1]'
        Info: Total cell delay = 2.124 ns ( 36.43 % )
        Info: Total interconnect delay = 3.706 ns ( 63.57 % )
Info: th for register "DipSwitch_flop1" (data pin = "DipSwitch", clock pin = "clk") is -4.613 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.902 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk'
        Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X14_Y2_N1; Fanout = 1; REG Node = 'DipSwitch_flop1'
        Info: Total cell delay = 2.180 ns ( 75.12 % )
        Info: Total interconnect delay = 0.722 ns ( 24.88 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.530 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_58; Fanout = 1; PIN Node = 'DipSwitch'
        Info: 2: + IC(5.946 ns) + CELL(0.115 ns) = 7.530 ns; Loc. = LC_X14_Y2_N1; Fanout = 1; REG Node = 'DipSwitch_flop1'
        Info: Total cell delay = 1.584 ns ( 21.04 % )
        Info: Total interconnect delay = 5.946 ns ( 78.96 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 112 megabytes of memory during processing
    Info: Processing ended: Mon May 11 21:25:13 2009
    Info: Elapsed time: 00:00:01