cai_lizi.vhd

vhdl32路彩灯设计 maxplus平台 比较齐全

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cai_lizi is 
port(ppclk:in std_logic;
     dzout:out integer range 0 to 122;
     pc:out std_logic);
end;
architecture lizi of cai_lizi is
signal count:integer range 0 to 122;
signal jiep:std_logic;
begin
p01:process(ppclk)
begin
if count=121 then count<=0; jiep<='1';
elsif rising_edge(ppclk)then count<=count+1; jiep<='0';
end if;
end process;
p02:process(jiep)
variable count2:std_logic;
begin 
if jiep'event and jiep='1'
then count2:=not count2;
end if;
if count2='1' then pc<='1';
else pc<='0';
end if;
end process;
dzout<=count;
end;