cai_lizi.rpt

vhdl32路彩灯设计 maxplus平台 比较齐全

cai_lizi

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (38)    20    B       DFFE   +  t        0      0   0    0    7    1    0  jiep (:17)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                              c:\work\cai_lizi.rpt
cai_lizi

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                           Logic cells placed in LAB 'B'
        +----------------- LC21 dzout0
        | +--------------- LC23 dzout1
        | | +------------- LC26 dzout2
        | | | +----------- LC24 dzout3
        | | | | +--------- LC19 dzout4
        | | | | | +------- LC18 dzout5
        | | | | | | +----- LC17 dzout6
        | | | | | | | +--- LC27 pc
        | | | | | | | | +- LC20 jiep
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC21 -> * * * * * * * - * | - * | <-- dzout0
LC23 -> * * * * * * * - * | - * | <-- dzout1
LC26 -> * * * * * * * - * | - * | <-- dzout2
LC24 -> * * * * * * * - * | - * | <-- dzout3
LC19 -> * * * * * * * - * | - * | <-- dzout4
LC18 -> * * * * * * * - * | - * | <-- dzout5
LC17 -> * * * * * * * - * | - * | <-- dzout6
LC20 -> - - - - - - - * - | - * | <-- jiep

Pin
43   -> - - - - - - - - - | - - | <-- ppclk


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                              c:\work\cai_lizi.rpt
cai_lizi

** EQUATIONS **

ppclk    : INPUT;

-- Node name is 'dzout0' = 'count0' 
-- Equation name is 'dzout0', location is LC021, type is output.
 dzout0  = TFFE( VCC, GLOBAL( ppclk), !_EQ001,  VCC,  VCC);
  _EQ001 =  dzout0 & !dzout1 & !dzout2 &  dzout3 &  dzout4 &  dzout5 & 
              dzout6;

-- Node name is 'dzout1' = 'count1' 
-- Equation name is 'dzout1', location is LC023, type is output.
 dzout1  = TFFE( dzout0, GLOBAL( ppclk), !_EQ002,  VCC,  VCC);
  _EQ002 =  dzout0 & !dzout1 & !dzout2 &  dzout3 &  dzout4 &  dzout5 & 
              dzout6;

-- Node name is 'dzout2' = 'count2' 
-- Equation name is 'dzout2', location is LC026, type is output.
 dzout2  = TFFE( _EQ003, GLOBAL( ppclk), !_EQ004,  VCC,  VCC);
  _EQ003 =  dzout0 &  dzout1;
  _EQ004 =  dzout0 & !dzout1 & !dzout2 &  dzout3 &  dzout4 &  dzout5 & 
              dzout6;

-- Node name is 'dzout3' = 'count3' 
-- Equation name is 'dzout3', location is LC024, type is output.
 dzout3  = TFFE( _EQ005, GLOBAL( ppclk), !_EQ006,  VCC,  VCC);
  _EQ005 =  dzout0 &  dzout1 &  dzout2;
  _EQ006 =  dzout0 & !dzout1 & !dzout2 &  dzout3 &  dzout4 &  dzout5 & 
              dzout6;

-- Node name is 'dzout4' = 'count4' 
-- Equation name is 'dzout4', location is LC019, type is output.
 dzout4  = TFFE( _EQ007, GLOBAL( ppclk), !_EQ008,  VCC,  VCC);
  _EQ007 =  dzout0 &  dzout1 &  dzout2 &  dzout3;
  _EQ008 =  dzout0 & !dzout1 & !dzout2 &  dzout3 &  dzout4 &  dzout5 & 
              dzout6;

-- Node name is 'dzout5' = 'count5' 
-- Equation name is 'dzout5', location is LC018, type is output.
 dzout5  = TFFE( _EQ009, GLOBAL( ppclk), !_EQ010,  VCC,  VCC);
  _EQ009 =  dzout0 &  dzout1 &  dzout2 &  dzout3 &  dzout4;
  _EQ010 =  dzout0 & !dzout1 & !dzout2 &  dzout3 &  dzout4 &  dzout5 & 
              dzout6;

-- Node name is 'dzout6' = 'count6' 
-- Equation name is 'dzout6', location is LC017, type is output.
 dzout6  = TFFE( _EQ011, GLOBAL( ppclk), !_EQ012,  VCC,  VCC);
  _EQ011 =  dzout0 &  dzout1 &  dzout2 &  dzout3 &  dzout4 &  dzout5;
  _EQ012 =  dzout0 & !dzout1 & !dzout2 &  dzout3 &  dzout4 &  dzout5 & 
              dzout6;

-- Node name is ':17' = 'jiep' 
-- Equation name is 'jiep', location is LC020, type is buried.
jiep     = DFFE( GND $  GND, GLOBAL( ppclk),  VCC, !_EQ013,  VCC);
  _EQ013 =  dzout0 & !dzout1 & !dzout2 &  dzout3 &  dzout4 &  dzout5 & 
              dzout6;

-- Node name is 'pc' = 'count2~149' 
-- Equation name is 'pc', location is LC027, type is output.
 pc      = TFFE( VCC,  jiep,  VCC,  VCC,  VCC);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                       c:\work\cai_lizi.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX3000A' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,814K