📄 cai_bmq.rpt
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Project Information c:\work\cai_bmq.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 04/28/2009 11:08:42
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
CAI_BMQ
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
cai_bmq EPM3128ATC100-5 7 32 0 69 60 53 %
User Pins: 7 32 0
Device-Specific Information: c:\work\cai_bmq.rpt
cai_bmq
***** Logic for device 'cai_bmq' compiled without errors.
Device: EPM3128ATC100-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffffffff
MultiVolt I/O = OFF
R R R R R R
E E E E E E
d d d d d S S S V q q S S S q q q
z z z z z E E E C o o E V E E o o o
o o o o o R R R C u u R C R R u u u
u u u u u G V V V I G G G G G t t V C V V t G t t
t t t t t N E E E N N N N N N 2 2 E I E E 2 N 1 3
5 4 3 2 1 D D D D T D D D D D 1 3 D O D D 0 D 9 1
----------------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 80 78 76 |_
/ 99 97 95 93 91 89 87 85 83 81 79 77 |
dzout6 | 1 75 | qout22
dzout0 | 2 74 | GND
VCCIO | 3 73 | #TDO
#TDI | 4 72 | qout7
RESERVED | 5 71 | qout6
RESERVED | 6 70 | qout12
RESERVED | 7 69 | qout3
RESERVED | 8 68 | qout4
RESERVED | 9 67 | qout5
RESERVED | 10 66 | VCCIO
GND | 11 65 | GND
RESERVED | 12 64 | qout10
RESERVED | 13 EPM3128ATC100-5 63 | qout8
RESERVED | 14 62 | #TCK
#TMS | 15 61 | RESERVED
RESERVED | 16 60 | RESERVED
RESERVED | 17 59 | GND
VCCIO | 18 58 | RESERVED
RESERVED | 19 57 | RESERVED
RESERVED | 20 56 | qout25
RESERVED | 21 55 | qout24
RESERVED | 22 54 | qout27
qout13 | 23 53 | GND
qout9 | 24 52 | qout14
qout11 | 25 51 | VCCIO
| 27 29 31 33 35 37 39 41 43 45 47 49 _|
\ 26 28 30 32 34 36 38 40 42 44 46 48 50 |
\-----------------------------------------------------
G R R R q R q G V q q q G V q R q G q R R R q q q
N E E E o E o N C o o o N C o E o N o E E E o o o
D S S S u S u D C u u u D C u S u D u S S S u u u
E E E t E t I t t t I t E t t E E E t t t
R R R 1 R 0 O 2 2 3 N 1 R 2 2 R R R 1 1 1
V V V V 9 0 T 5 V 8 6 V V V 8 7 6
E E E E E E E E
D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\work\cai_bmq.rpt
cai_bmq
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 7/10( 70%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 1/10( 10%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 3/16( 18%) 4/10( 40%) 15/16( 93%) 10/36( 27%)
D: LC49 - LC64 7/16( 43%) 5/ 9( 55%) 6/16( 37%) 14/36( 38%)
E: LC65 - LC80 14/16( 87%) 6/10( 60%) 16/16(100%) 19/36( 52%)
F: LC81 - LC96 15/16( 93%) 5/ 9( 55%) 16/16(100%) 13/36( 36%)
G: LC97 - LC112 15/16( 93%) 9/ 9(100%) 16/16(100%) 19/36( 52%)
H: LC113 - LC128 15/16( 93%) 6/ 9( 66%) 14/16( 87%) 18/36( 50%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 43/76 ( 56%)
Total logic cells used: 69/128 ( 53%)
Total shareable expanders used: 60/128 ( 46%)
Total Turbo logic cells used: 69/128 ( 53%)
Total shareable expanders not available (n/a): 23/128 ( 17%)
Average fan-in: 7.57
Total fan-in: 523
Total input pins required: 7
Total output pins required: 32
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 69
Total flipflops required: 0
Total product terms required: 280
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 46
Synthesized logic cells: 37/ 128 ( 28%)
Device-Specific Information: c:\work\cai_bmq.rpt
cai_bmq
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
2 (1) (A) INPUT 0 0 0 0 0 30 22 dzout0
96 (11) (A) INPUT 0 0 0 0 0 31 20 dzout1
97 (9) (A) INPUT 0 0 0 0 0 31 28 dzout2
98 (8) (A) INPUT 0 0 0 0 0 31 31 dzout3
99 (6) (A) INPUT 0 0 0 0 0 31 36 dzout4
100 (5) (A) INPUT 0 0 0 0 0 32 33 dzout5
1 (3) (A) INPUT 0 0 0 0 0 31 34 dzout6
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\work\cai_bmq.rpt
cai_bmq
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
32 56 D OUTPUT t 0 0 0 7 0 0 0 qout0
30 59 D OUTPUT t 2 2 0 7 2 0 0 qout1
35 53 D OUTPUT t 3 3 0 7 2 0 0 qout2
69 105 G OUTPUT t 2 1 1 7 3 0 0 qout3
68 104 G OUTPUT t 3 2 1 7 4 0 0 qout4
67 102 G OUTPUT t 2 1 1 7 4 0 0 qout5
71 109 G OUTPUT t 2 1 1 7 5 0 0 qout6
72 110 G OUTPUT t 2 2 0 7 4 0 0 qout7
63 97 G OUTPUT t 3 0 1 7 0 0 0 qout8
24 35 C OUTPUT t 6 4 0 7 3 0 0 qout9
64 99 G OUTPUT t 3 2 1 7 3 0 0 qout10
25 33 C OUTPUT t 6 2 1 7 3 0 0 qout11
70 107 G OUTPUT t 3 2 1 7 2 0 0 qout12
23 37 C OUTPUT t 5 2 1 7 3 0 0 qout13
52 81 F OUTPUT t 5 2 0 7 2 0 0 qout14
40 65 E OUTPUT t 4 1 1 7 2 0 0 qout15
50 80 E OUTPUT t 2 1 1 7 3 0 0 qout16
49 78 E OUTPUT t 3 1 1 7 4 0 0 qout17
48 77 E OUTPUT t 6 4 1 7 4 0 0 qout18
77 117 H OUTPUT t 4 2 1 7 4 0 0 qout19
79 120 H OUTPUT t 2 1 1 7 8 0 0 qout20
85 128 H OUTPUT t 3 1 1 7 7 0 0 qout21
75 113 H OUTPUT t 3 2 1 7 8 0 0 qout22
84 126 H OUTPUT t 5 4 0 7 2 0 0 qout23
55 86 F OUTPUT t 5 3 1 7 2 0 0 qout24
56 88 F OUTPUT t 4 2 1 7 4 0 0 qout25
44 70 E OUTPUT t 0 0 0 1 3 0 0 qout26
54 85 F OUTPUT t 4 2 1 7 3 0 0 qout27
42 69 E OUTPUT t 1 1 0 6 3 0 0 qout28
36 51 D OUTPUT t 3 3 0 7 3 0 0 qout29
37 49 D OUTPUT t 2 2 0 7 2 0 0 qout30
76 115 H OUTPUT t 1 1 0 7 0 0 0 qout31
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\work\cai_bmq.rpt
cai_bmq
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 118 H SOFT s t 0 0 0 7 0 1 0 ~14310~1
- 127 H SOFT s t 0 0 0 7 0 2 0 ~14676~1
- 124 H SOFT s t 0 0 0 7 0 1 0 ~14676~2
(81) 123 H SOFT s t 0 0 0 6 0 1 0 ~15042~1
- 114 H SOFT s t 0 0 0 6 0 2 0 ~15042~2
(46) 73 E SOFT s t 1 0 1 7 0 1 0 ~15774~1
- 100 G SOFT s t 0 0 0 6 0 2 0 ~15774~2
- 116 H SOFT s t 0 0 0 7 0 1 0 ~15774~3
- 103 G SOFT s t 0 0 0 5 0 1 0 ~17238~1
- 108 G SOFT s t 0 0 0 6 0 1 0 ~17970~1
(60) 93 F SOFT s t 0 0 0 4 0 4 0 ~17970~2
(57) 89 F SOFT s t 0 0 0 5 0 3 0 ~18336~1
- 83 F SOFT s t 0 0 0 4 0 6 0 ~18336~2
- 87 F SOFT s t 0 0 0 4 0 4 0 ~18336~3
(61) 94 F SOFT s t 0 0 0 5 0 2 0 ~19068~1
- 98 G SOFT s t 0 0 0 6 0 1 0 ~19434~1
- 68 E SOFT s t 0 0 0 3 0 6 0 ~19434~2
- 90 F SOFT s t 0 0 0 5 0 3 0 ~20166~1
- 95 F SOFT s t 0 0 0 4 0 7 0 ~20166~2
- 84 F SOFT s t 0 0 0 5 0 1 0 ~20898~1
(80) 121 H SOFT s t 0 0 0 7 0 1 0 ~21630~1
(41) 67 E SOFT s t 0 0 0 4 0 4 0 ~21630~2
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