spwm_tb.vhd

VHDL采用自然采样法写的SPWM

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-- Company: 
-- Engineer:
--
-- Create Date:   09:13:30 05/18/2009
-- Design Name:   
-- Module Name:   G:/PRO/spwm1/SPWM_TB.vhd
-- Project Name:  spwm1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: SPWM
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY SPWM_TB IS
END SPWM_TB;
 
ARCHITECTURE behavior OF SPWM_TB IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT SPWM
    PORT(
         CLK : IN  std_logic;
         RESET : IN  std_logic;
         PUT_HZ : IN  std_logic_vector(7 downto 0);
         PUT_ff : IN  std_logic_vector(7 downto 0);
         A1_RESULT : OUT  std_logic;
         A2_RESULT : OUT  std_logic;
         B1_RESULT : OUT  std_logic;
         B2_RESULT : OUT  std_logic;
         C1_RESULT : OUT  std_logic;
         C2_RESULT : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal RESET : std_logic := '0';
   signal PUT_HZ : std_logic_vector(7 downto 0) := (others => '0');
   signal PUT_ff : std_logic_vector(7 downto 0) := (others => '0');

 	--Outputs
   signal A1_RESULT : std_logic;
   signal A2_RESULT : std_logic;
   signal B1_RESULT : std_logic;
   signal B2_RESULT : std_logic;
   signal C1_RESULT : std_logic;
   signal C2_RESULT : std_logic;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: SPWM PORT MAP (
          CLK => CLK,
          RESET => RESET,
          PUT_HZ => PUT_HZ,
          PUT_ff => PUT_ff,
          A1_RESULT => A1_RESULT,
          A2_RESULT => A2_RESULT,
          B1_RESULT => B1_RESULT,
          B2_RESULT => B2_RESULT,
          C1_RESULT => C1_RESULT,
          C2_RESULT => C2_RESULT
        );
CLK<= NOT CLK after 10 ns;
RESET <='1','0'after 15 ns,'1' after 50 ns;
put_hz<="11110000";
put_FF<="11111111";
END;