ctrl.txt

全数字锁相环（adpll)的部分源程序代码

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_arith.all; 
entity ctrl is
port ( idclk,reset:in std_logic; 
       inc,dec:in std_logic; 
         idout:out std_logic ); 
end ctrl;
architecture rtl of ctrl is
component dff2
port ( d,clk,clrn:in std_logic; 
       q,qn: out std_logic );
 end component;     
 component jkff2
port  ( j,k,clk,clrn:in std_logic; 
       q,qn: out std_logic );  
end component;  
signal q1,q1n,q2,q2n,q3,q3n,q4,q4n,q5,q5n:std_logic;
signal q6,q6n,q7,q7n,q8,q8n,q9,q9n,d7,d8:std_logic;
begin
ffd1:dff2 port map(inc,idclk,reset,q1,q1n);
ffd2:dff2 port map(dec,idclk,reset,q2,q2n);
ffd3:dff2 port map(q1,idclk,reset,q3,q3n);
ffd4:dff2 port map(q2,idclk,reset,q4,q4n);
ffd5:dff2 port map(q3,idclk,reset,q5,q5n);
ffd6:dff2 port map(q4,idclk,reset,q6,q6n);
d7<=(q9 and q1n and q3)or(q9 and q5 and q3n);
d8<=(q9n and q2n and q4)or(q9 and q6 and q4n);
ffd7:dff2 port map(d7,idclk,reset,q7,q7n);
ffd8:dff2 port map(q8,idclk,reset,q8,q8n);
jk:jkff2 port map(q7n,q8n,idclk,reset,q9,q9n);
idout<=idclk nor q9;
end rtl;