kcount.txt

全数字锁相环（adpll)的部分源程序代码

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity kcount is 
port ( 
      clk,updn,en,d,c,b,a:in std_logic; 
      up,dn:out std_logic 
      ); 
end kcount; 
architecture kcount_arch of kcount is 
signal cq,k,m:std_logic_vector(16 downto 0); 
signal out1,out2:std_logic; 
signal dir:std_logic_vector(3 downto 0); 
begin 
dir<=d&c&b&a; 
with dir select 
m<="0000000000000111"when"0001", 
   "0000000000001111"when"0010", 
   "0000000000011111"when"0011", 
   "0000000000111111"when"0100", 
   "0000000001111111"when"0101", 
   "0000000011111111"when"0110", 
   "0000000111111111"when"0111", 
   "0000001111111111"when"1000", 
   "0000011111111111"when"1001", 
   "0000111111111111"when"1010", 
   "0001111111111111"when"1011", 
   "0011111111111111"when"1100", 
   "0111111111111111"when"1101", 
   "1111111111111111"when"1110", 
   "0000000000000111"when others; 
   process(clk,en,updn,k,cq) 
begin 
if clk'event and clk='1' then 
k<=m; 
if en='1' then 
if updn='0' then 
if cq<k then cq<=cq+1; 
else cq<=(others=>'0'); 
end if; 
else 
if cq>0 then cq<=cq-1; 
else cq<=k; 
end if; 
end if; 
else cq<=(others=>'0'); 
end if; 
end if; 
end process; 
process(en,updn,cq,k) 
begin 
if en='1' then 
if updn='0' then 
if cq=k then out1<='1'; 
else out1<='0'; 
end if; 
out2 <='0'; 
else 
if cq="00000000000000000"then out2<='1'; 
else out2<='0'; 
end if; 
out1<='0'; 
end if; 
else out1<='0';out2<='0'; 
end if; 
end process; 
up<=out1;dn<=out2; 
end kcount_arch;