adder16b.vhd

来自「dds 用vhdl语言写成」· VHDL 代码 · 共 13 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder16b is
 port(a:in std_logic_vector(15 downto 0);
      b:in std_logic_vector(15 downto 0);
      s:out std_logic_vector(15 downto 0));
end  adder16b;
architecture behav of adder16b is 
 begin
 s<=a+b;
end behav;