📄 adder16b.rpt
字号:
79 - - - 24 OUTPUT 0 1 0 0 s4
66 - - B -- OUTPUT 0 1 0 0 s5
67 - - B -- OUTPUT 0 1 0 0 s6
65 - - B -- OUTPUT 0 1 0 0 s7
19 - - A -- OUTPUT 0 1 0 0 s8
6 - - - 04 OUTPUT 0 1 0 0 s9
18 - - A -- OUTPUT 0 1 0 0 s10
78 - - - 24 OUTPUT 0 1 0 0 s11
69 - - A -- OUTPUT 0 1 0 0 s12
72 - - A -- OUTPUT 0 1 0 0 s13
80 - - - 23 OUTPUT 0 1 0 0 s14
60 - - C -- OUTPUT 0 1 0 0 s15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\electronics\muxflie\dds_vhdl\adder16b.rpt
adder16b
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - C 23 OR2 4 0 0 2 |LPM_ADD_SUB:49|addcore:adder|pcarry1
- 6 - C 23 OR2 2 1 0 2 |LPM_ADD_SUB:49|addcore:adder|pcarry2
- 2 - C 23 OR2 2 1 0 2 |LPM_ADD_SUB:49|addcore:adder|pcarry3
- 2 - B 23 OR2 2 1 0 2 |LPM_ADD_SUB:49|addcore:adder|pcarry4
- 4 - B 23 OR2 2 1 0 2 |LPM_ADD_SUB:49|addcore:adder|pcarry5
- 7 - B 23 OR2 2 1 0 2 |LPM_ADD_SUB:49|addcore:adder|pcarry6
- 6 - B 23 OR2 2 1 0 2 |LPM_ADD_SUB:49|addcore:adder|pcarry7
- 3 - A 04 OR2 2 1 0 2 |LPM_ADD_SUB:49|addcore:adder|pcarry8
- 4 - A 04 OR2 2 1 0 2 |LPM_ADD_SUB:49|addcore:adder|pcarry9
- 1 - A 04 OR2 2 1 0 2 |LPM_ADD_SUB:49|addcore:adder|pcarry10
- 4 - A 24 OR2 2 1 0 2 |LPM_ADD_SUB:49|addcore:adder|pcarry11
- 5 - A 24 OR2 2 1 0 2 |LPM_ADD_SUB:49|addcore:adder|pcarry12
- 6 - A 24 OR2 2 1 0 2 |LPM_ADD_SUB:49|addcore:adder|pcarry13
- 1 - A 24 OR2 2 1 0 1 |LPM_ADD_SUB:49|addcore:adder|pcarry14
- 3 - C 23 OR2 2 0 1 0 |LPM_ADD_SUB:49|addcore:adder|:161
- 7 - C 23 OR2 4 0 1 0 |LPM_ADD_SUB:49|addcore:adder|:178
- 5 - C 23 OR2 2 1 1 0 |LPM_ADD_SUB:49|addcore:adder|:179
- 1 - C 23 OR2 2 1 1 0 |LPM_ADD_SUB:49|addcore:adder|:180
- 8 - B 23 OR2 2 1 1 0 |LPM_ADD_SUB:49|addcore:adder|:181
- 3 - B 23 OR2 2 1 1 0 |LPM_ADD_SUB:49|addcore:adder|:182
- 1 - B 23 OR2 2 1 1 0 |LPM_ADD_SUB:49|addcore:adder|:183
- 5 - B 23 OR2 2 1 1 0 |LPM_ADD_SUB:49|addcore:adder|:184
- 6 - A 04 OR2 2 1 1 0 |LPM_ADD_SUB:49|addcore:adder|:185
- 2 - A 04 OR2 2 1 1 0 |LPM_ADD_SUB:49|addcore:adder|:186
- 8 - A 04 OR2 2 1 1 0 |LPM_ADD_SUB:49|addcore:adder|:187
- 3 - A 24 OR2 2 1 1 0 |LPM_ADD_SUB:49|addcore:adder|:188
- 7 - A 24 OR2 2 1 1 0 |LPM_ADD_SUB:49|addcore:adder|:189
- 2 - A 24 OR2 2 1 1 0 |LPM_ADD_SUB:49|addcore:adder|:190
- 8 - A 24 OR2 2 1 1 0 |LPM_ADD_SUB:49|addcore:adder|:191
- 4 - C 17 OR2 2 1 1 0 |LPM_ADD_SUB:49|addcore:adder|:192
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\electronics\muxflie\dds_vhdl\adder16b.rpt
adder16b
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 9/ 96( 9%) 5/ 48( 10%) 6/ 48( 12%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
B: 6/ 96( 6%) 0/ 48( 0%) 6/ 48( 12%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
C: 5/ 96( 5%) 0/ 48( 0%) 5/ 48( 10%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\electronics\muxflie\dds_vhdl\adder16b.rpt
adder16b
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
a4 : INPUT;
a5 : INPUT;
a6 : INPUT;
a7 : INPUT;
a8 : INPUT;
a9 : INPUT;
a10 : INPUT;
a11 : INPUT;
a12 : INPUT;
a13 : INPUT;
a14 : INPUT;
a15 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
b4 : INPUT;
b5 : INPUT;
b6 : INPUT;
b7 : INPUT;
b8 : INPUT;
b9 : INPUT;
b10 : INPUT;
b11 : INPUT;
b12 : INPUT;
b13 : INPUT;
b14 : INPUT;
b15 : INPUT;
-- Node name is 's0'
-- Equation name is 's0', type is output
s0 = _LC3_C23;
-- Node name is 's1'
-- Equation name is 's1', type is output
s1 = _LC7_C23;
-- Node name is 's2'
-- Equation name is 's2', type is output
s2 = _LC5_C23;
-- Node name is 's3'
-- Equation name is 's3', type is output
s3 = _LC1_C23;
-- Node name is 's4'
-- Equation name is 's4', type is output
s4 = _LC8_B23;
-- Node name is 's5'
-- Equation name is 's5', type is output
s5 = _LC3_B23;
-- Node name is 's6'
-- Equation name is 's6', type is output
s6 = _LC1_B23;
-- Node name is 's7'
-- Equation name is 's7', type is output
s7 = _LC5_B23;
-- Node name is 's8'
-- Equation name is 's8', type is output
s8 = _LC6_A4;
-- Node name is 's9'
-- Equation name is 's9', type is output
s9 = _LC2_A4;
-- Node name is 's10'
-- Equation name is 's10', type is output
s10 = _LC8_A4;
-- Node name is 's11'
-- Equation name is 's11', type is output
s11 = _LC3_A24;
-- Node name is 's12'
-- Equation name is 's12', type is output
s12 = _LC7_A24;
-- Node name is 's13'
-- Equation name is 's13', type is output
s13 = _LC2_A24;
-- Node name is 's14'
-- Equation name is 's14', type is output
s14 = _LC8_A24;
-- Node name is 's15'
-- Equation name is 's15', type is output
s15 = _LC4_C17;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_C23', type is buried
_LC4_C23 = LCELL( _EQ001);
_EQ001 = a1 & b1
# a0 & a1 & b0
# a0 & b0 & b1;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_C23', type is buried
_LC6_C23 = LCELL( _EQ002);
_EQ002 = a2 & _LC4_C23
# b2 & _LC4_C23
# a2 & b2;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_C23', type is buried
_LC2_C23 = LCELL( _EQ003);
_EQ003 = b3 & _LC6_C23
# a3 & _LC6_C23
# a3 & b3;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_B23', type is buried
_LC2_B23 = LCELL( _EQ004);
_EQ004 = b4 & _LC2_C23
# a4 & _LC2_C23
# a4 & b4;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_B23', type is buried
_LC4_B23 = LCELL( _EQ005);
_EQ005 = b5 & _LC2_B23
# a5 & _LC2_B23
# a5 & b5;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_B23', type is buried
_LC7_B23 = LCELL( _EQ006);
_EQ006 = b6 & _LC4_B23
# a6 & _LC4_B23
# a6 & b6;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|pcarry7' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_B23', type is buried
_LC6_B23 = LCELL( _EQ007);
_EQ007 = b7 & _LC7_B23
# a7 & _LC7_B23
# a7 & b7;
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