carry_or.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: carry_or.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- carry_or.vhd - Entity and architecture
--
--  ***************************************************************************
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--  **  standard level Xilinx Hotline support, and will only address         **
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--
-------------------------------------------------------------------------------
-- Filename:        carry_or.vhd
--
-- Description:     one bit OR function using carry-chain
--                  
-- VHDL-Standard:   VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:   
--              carry_or.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2006-08-09    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

library unisim;
use unisim.vcomponents.all;

entity carry_or is
  generic (
    C_TARGET : TARGET_FAMILY_TYPE
    );
  port (
    Carry_IN  : in  std_logic;
    A         : in  std_logic;
    Carry_OUT : out std_logic);
end entity carry_or;

architecture IMP of carry_or is
  signal carry_out_i : std_logic;
  attribute keep : string;
  attribute keep of carry_out_i : signal is "TRUE";
  
begin  -- architecture IMP

  -----------------------------------------------------------------------------
  -- FPGA implementation
  -----------------------------------------------------------------------------
  Using_FPGA : if (C_TARGET /= RTL) generate
    signal A_N : std_logic;
  begin
    A_N <= not A;
    MUXCY_I : MUXCY_L
      port map (
        DI => '1',
        CI => Carry_IN,
        S  => A_N,
        LO => carry_out_i);
    Carry_OUT <= carry_out_i;
  end generate Using_FPGA;

  -----------------------------------------------------------------------------
  -- RTL Implementation
  -----------------------------------------------------------------------------
  Using_RTL: if (C_TARGET = RTL) generate
    Carry_OUT <= '1' when A = '1' else Carry_IN;
  end generate Using_RTL;
end architecture IMP;