carry_compare_mask.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

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-- $Id: carry_compare_mask.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
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-- Carry_compare_mask.vhd - Entity and architecture
--
--  ***************************************************************************
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--
-------------------------------------------------------------------------------
-- Filename:        carry_compare_mask.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              carry_compare_mask.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2007-06-12    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

entity carry_compare_mask is
  generic (
    C_TARGET : TARGET_FAMILY_TYPE;
    Size     : natural);
  port (
    A_Vec      : in  std_logic_vector(0 to Size-1);
    B_Vec      : in  std_logic_vector(0 to Size-1);
    Mask       : in  std_logic_vector(0 to Size-1);
    Carry_In   : in  std_logic;
    Carry_Out  : out std_logic);
end entity carry_compare_mask;

library unisim;
use unisim.vcomponents.all;

architecture IMP of carry_compare_mask is

  component carry_and is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE);
    port (
      Carry_IN  : in  std_logic;
      A         : in  std_logic;
      Carry_OUT : out std_logic);
  end component carry_and;

  constant C_BITS_PER_LUT : integer:= (Family_To_LUT_Size(C_TARGET) / 3);

  signal sel   : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT) - 1);
  signal carry : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT));

  signal A : std_logic_vector(0 to sel'length*C_BITS_PER_LUT - 1);
  signal B : std_logic_vector(0 to sel'length*C_BITS_PER_LUT - 1);
  signal M : std_logic_vector(0 to sel'length*C_BITS_PER_LUT - 1);

begin  -- architecture IMP

  assign_sigs : process (A_Vec, B_Vec, Mask) is
  begin  -- process assign_sigs
    A              <= (others => '1');
    A(0 to Size-1) <= A_Vec;
    B              <= (others => '1');
    B(0 to Size-1) <= B_Vec;
    M              <= (others => '1');
    M(0 to Size-1) <= Mask;
  end process assign_sigs;

  carry(carry'right) <= Carry_In;

  The_Compare : for I in sel'right downto sel'left generate
  begin
    -- Combine the signals that fit into one LUT.
--    sel(I) <= not(Mask(I)) or (A_Vec(I) xnor B_Vec(I));
    Compare_All_Bits: process(A,B,M)
      variable sel_I   : std_logic;
    begin
      sel_I  :=  '1';
      Compare_Bits: for J in C_BITS_PER_LUT - 1 downto 0 loop
        sel_I  := sel_I and ( not(M(C_BITS_PER_LUT * I + J)) or ( A(C_BITS_PER_LUT * I + J) xnor B(C_BITS_PER_LUT * I + J) ) );
      end loop Compare_Bits;
      sel(I) <= sel_I;
    end process Compare_All_Bits;

    carry_and_I1: carry_and
      generic map (
        C_TARGET => C_TARGET)     -- [TARGET_FAMILY_TYPE]
      port map (
        Carry_IN  => Carry(I+1),  -- [in  std_logic]
        A         => sel(I),      -- [in  std_logic]
        Carry_OUT => Carry(I));   -- [out std_logic]

  end generate The_Compare;

  Carry_Out <= Carry(0);

end architecture IMP;