operand_select_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: operand_select_gti.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- operand_select.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2001-2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc. 
-- **
-- ** Unmodified source code is guaranteed to place and route, 
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: operand_select.vhd
-- Version: v2.00a
-- Description: Selects which operands are used for the instruction
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              operand_select.vhd
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--   BJS    2005-03-24
-- ^^^^^^
--                        Updated for new pipeline
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY_>I_<#|FUNC>" , "ENTITY>_I#" 
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                      -- instruction fetch
--    OF                      -- operand fetch
--    EX                      -- execute
--    MEM                     -- memory
--    WB                      -- write back
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types and ISA constants
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
--
--    C_TARGET                -- Device family
--
-- Definition of Ports:
--
--    Clk                     -- Clock
--    Reset                   -- internal reset
--
--    OF_PipeRun              -- Move the operand fetch stage
--
--    GPR_Op1                 -- General Purpose Register operand 1
--    GPR_Op2                 -- General Purpose Register operand 2
--    GPR_Op3                 -- General Purpose Register operand 3
-- 
--    OF_Imm_Data             -- Opcode immediate data
--    OF_Write_Imm_Reg        -- Immediate register write strobe
--    OF_Read_Imm_Reg         -- Immediate register read strobe
--
--    OF_PC                   -- Operand Fetch stage program counter
--    OF_Op1_Sel_PC           -- Op1 select program counter
--
--    EX_Fwd                  -- Execute stage forwarding
--    MEM_Fwd                 -- Memory stage forwarding
--    WB_Fwd                  -- Write back stage forwarding
--
--    OF_Op1_Sel              -- Op1 select 
--    OF_Op2_Sel              -- Op2 select 
--    OF_Op3_Sel              -- Op3 select 
--
--    EX_Op1                  -- Execute stage operand 1
--    EX_Op2                  -- Execute stage operand 2
--    EX_Op3                  -- Execute stage operand 3
--                               (Data to be written that needs to be mirrored)
--
--    EX_Branch_CMP_Op1       -- Execute stage operand 1 with out the SPR muxed in
--                               (Used by zero detect for branches, which also need Op1 for PC)
--
-------------------------------------------------------------------------------

library microblaze_v7_10_a;
use microblaze_v7_10_a.microblaze_isa.all;

entity Operand_Select_gti is
  generic (
    C_TARGET : TARGET_FAMILY_TYPE
  );
  port (
    Clk   : in std_logic;
    Reset : in std_logic;

    OF_PipeRun : in boolean;

    GPR_Op1 : in DATA_TYPE;
    GPR_Op2 : in DATA_TYPE;
    GPR_Op3 : in DATA_TYPE;

    OF_Imm_Data       : in IMM16_TYPE;
    OF_Write_Imm_Reg  : in boolean;
    OF_Read_Imm_Reg   : in boolean;
    OF_Take_Interrupt : in boolean;
    OF_Take_Ext_BRK   : in boolean;
    OF_Take_Exception : in boolean;

    OF_PC  : in DATA_TYPE;
    EX_MSR : in DATA_TYPE;

    EX_Fwd  : in DATA_TYPE;
    MEM_Fwd : in DATA_TYPE;
    WB_Fwd  : in DATA_TYPE;

    OF_Op1_Sel_SPR_PC  : in boolean;
    OF_Op1_Sel_SPR_MSR : in boolean;
    OF_Op1_Sel_SPR     : in boolean;
    OF_Op2_Sel_Imm     : in boolean;
    OF_Op1_Sel         : in std_logic_vector(0 to 1);

    OF_Op2_Sel : in std_logic_vector(0 to 1);

    OF_Op3_Sel : in std_logic_vector(0 to 1);

    EX_Op1 : out DATA_TYPE;
    EX_Op2 : out DATA_TYPE;
    EX_Op3 : out DATA_TYPE;

    EX_Branch_CMP_Op1 : out DATA_TYPE

    -- EX_OpSel_Op2_cpy        : out DATA_TYPE;

    -- Take_Interrupt          : in  boolean;
    -- Take_Ext_BRK            : in  boolean;
    -- Take_Exception          : in  boolean;

    -- word_r1_r2_unalignment  : out std_logic;
    -- word_r1_imm_unalignment : out std_logic;
    -- halfword_unalignment    : out std_logic
    );

end entity Operand_Select_gti;

--------------------------------------------------------------------------
-- Architecture section
--------------------------------------------------------------------------

architecture IMP of Operand_Select_gti is

  signal of_branch_cmp : DATA_TYPE;

  signal of_op1        : DATA_TYPE;
  signal of_op2        : DATA_TYPE;
  signal of_op3        : DATA_TYPE;

  signal of_spr        : DATA_TYPE;
  
  signal op2_imm       : DATA_TYPE;
  signal sign_imm      : DATA_TYPE;
  signal extend_imm    : DATA_TYPE;

  ---------------------
  -- Immediate Register
  ---------------------
  signal imm_reg       : IMM16_TYPE;
begin

  --***************************************************************************
  --***************************************************************************
  --                   Operand Fetch (OF) stage handling