wb_mux_bit_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

                ( ( not WB_Exception_Taken ) and ( WB_Fwd_I1    or Data_Bits(6) or 
                                                   Data_Bits(7) or WB_Fwd_I2    ) );
      
    end generate Using_WB6_10_14_Size;
    
    ----------------------------------------
    -- WB mux with other number of inputs
    ----------------------------------------
    Using_WB6_Other_Size: if( Data_Bits'length > 14 ) generate
    begin
      WB_Fwd <= ( (     WB_Exception_Taken ) and WB_PC                ) or
                ( ( not WB_Exception_Taken ) and Vector_OR(Data_Bits) );
  
    end generate Using_WB6_Other_Size;
  
  end generate Using_LUT6_Based;
  
  
  
  
  -- -------------------------------------------------------------------------
  -- USE LUT4 BASED ARCHITECTURES
  -- -------------------------------------------------------------------------
  Using_LUT4_Based: if( not USE_LUT6_BASED ) generate
  begin
    ----------------------------------------
    -- WB mux with 1-2 inputs
    ----------------------------------------
    Using_WB_1_2_Size: if( Data_Bits'length >= 1 and Data_Bits'length <= 2 ) generate
    begin
      -- Implemented as 1 LUT.
      -- => 1 logic level.
      --
      WB_Fwd <= ( (     WB_Exception_Taken ) and WB_PC                ) or
                ( ( not WB_Exception_Taken ) and Vector_OR(Data_Bits) );
  
    end generate Using_WB_1_2_Size;
  
  
    ----------------------------------------
    -- WB mux with 3-4 inputs
    ----------------------------------------
    Using_WB_3_4_Size: if( Data_Bits'length >= 3 and Data_Bits'length <= 4 ) generate
      
      signal WB_Fwd_I1  : std_logic;
      
    begin
      -- Implemented as 1 LUT -> 1 MUXF5.
      -- => 1 logic level.
      --
      WB_Fwd_I1 <= Vector_OR(Data_Bits);
      
      MUXF5_3_4 : MUXF5
      port map (
        O  => WB_Fwd,              -- [out std_logic]
        I0 => WB_Fwd_I1,           -- [in  std_logic]
        I1 => WB_PC,               -- [in  std_logic]
        S  => WB_Exception_Taken   -- [in  std_logic]
      );
      
    end generate Using_WB_3_4_Size;
  
  
    ----------------------------------------
    -- WB mux with 5-8 inputs
    ----------------------------------------
    Using_WB_5_8_Size: if( Data_Bits'length >= 5 and Data_Bits'length <= 8 ) generate
      
      signal WB_Fwd_I1  : std_logic;
      signal WB_Fwd_I2  : std_logic;
      signal WB_Fwd_I   : std_logic;
      
    begin
      -- Implemented as 2 LUT -> 2 MUXF5.
      -- => 1 logic level.
      -- (Uses one external LUT to select group one)
      --
      WB_Fwd_I2 <= Vector_OR(Data_Bits(0 to 3));
      WB_Fwd_I1 <= Vector_OR(Data_Bits(4 to Data_Bits'right));
      
      MUXF5_5_8 : MUXF5
      port map (
        O  => WB_Fwd_I,            -- [out std_logic]
        I0 => WB_Fwd_I1,           -- [in  std_logic]
        I1 => WB_Fwd_I2,           -- [in  std_logic]
        S  => Select_Bits(0)       -- [in  std_logic]
      );
      
      MUXF6_5_8 : MUXF6
      port map (
        O  => WB_Fwd,              -- [out std_logic]
        I0 => WB_Fwd_I,            -- [in  std_logic]
        I1 => WB_PC,               -- [in  std_logic]
        S  => WB_Exception_Taken   -- [in  std_logic]
      );
      
    end generate Using_WB_5_8_Size;
  
  
    ----------------------------------------
    -- WB mux with 9 inputs
    ----------------------------------------
    Using_WB_9_Size: if( Data_Bits'length = 9 ) generate
      
      signal WB_Fwd_I1  : std_logic;
      signal WB_Fwd_I2  : std_logic;
      signal WB_Fwd_I   : std_logic;
      
    begin
      -- Implemented as 2 LUT -> 1 MUXF5 -> 1 LUT.
      -- => 2 logic levels.
      -- (Uses one external LUT to select group one)
      --
      WB_Fwd_I2 <= Vector_OR(Data_Bits(0 to 3));
      WB_Fwd_I1 <= Vector_OR(Data_Bits(4 to 7));
      
      MUXF5_5_8 : MUXF5
      port map (
        O  => WB_Fwd_I,            -- [out std_logic]
        I0 => WB_Fwd_I1,           -- [in  std_logic]
        I1 => WB_Fwd_I2,           -- [in  std_logic]
        S  => Select_Bits(0)       -- [in  std_logic]
      );
      
      WB_Fwd <= ( (     WB_Exception_Taken ) and ( WB_PC                    ) ) or
                ( ( not WB_Exception_Taken ) and ( WB_Fwd_I or Data_Bits(8) ) );
      
    end generate Using_WB_9_Size;
  
  
    ----------------------------------------
    -- WB mux with 10-12 inputs
    ----------------------------------------
    Using_WB_10_12_Size: if( Data_Bits'length >= 10 and Data_Bits'length <= 12 ) generate
      
      signal WB_Fwd_I1  : std_logic;
      signal WB_Fwd_I2  : std_logic;
      signal WB_Fwd_I3  : std_logic;
      signal WB_Fwd_I   : std_logic;
      
    begin
      -- Implemented as 3 LUT -> 1 MUXF5 -> 1 LUT.
      -- => 2 logic levels.
      -- (Uses one external LUT to select group one)
      --
      WB_Fwd_I2 <= Vector_OR(Data_Bits(0 to 3));
      WB_Fwd_I1 <= Vector_OR(Data_Bits(4 to 7));
      WB_Fwd_I3 <= Vector_OR(Data_Bits(8 to Data_Bits'right));
      
      MUXF5_5_8 : MUXF5
      port map (
        O  => WB_Fwd_I,            -- [out std_logic]
        I0 => WB_Fwd_I1,           -- [in  std_logic]
        I1 => WB_Fwd_I2,           -- [in  std_logic]
        S  => Select_Bits(0)       -- [in  std_logic]
      );
      
      WB_Fwd <= ( (     WB_Exception_Taken ) and ( WB_PC                 ) ) or
                ( ( not WB_Exception_Taken ) and ( WB_Fwd_I or WB_Fwd_I3 ) );
      
    end generate Using_WB_10_12_Size;
  
  
    ----------------------------------------
    -- WB mux with 13-16 inputs
    ----------------------------------------
    Using_WB_13_16_Size: if( Data_Bits'length >= 13 and Data_Bits'length <= 16 ) generate
      
      signal WB_Fwd_I1  : std_logic;
      signal WB_Fwd_I2  : std_logic;
      signal WB_Fwd_I3  : std_logic;
      signal WB_Fwd_I4  : std_logic;
      signal WB_Fwd_I   : std_logic;
      signal WB_Fwd_II  : std_logic;
      
    begin
      -- Implemented as 4 LUT -> 2 MUXF5 -> 1 LUT.
      -- => 2 logic levels.
      -- (Uses one external LUT to select group one or three)
      --
      WB_Fwd_I2 <= Vector_OR(Data_Bits(0 to 3));
      WB_Fwd_I1 <= Vector_OR(Data_Bits(4 to 7));
      WB_Fwd_I4 <= Vector_OR(Data_Bits(8 to 11));
      WB_Fwd_I3 <= Vector_OR(Data_Bits(12 to Data_Bits'right));
      
      MUXF5_13_16_1: MUXF5
      port map (
        O  => WB_Fwd_I,            -- [out std_logic]
        I0 => WB_Fwd_I1,           -- [in  std_logic]
        I1 => WB_Fwd_I2,           -- [in  std_logic]
        S  => Select_Bits(0)       -- [in  std_logic]
      );
      
      MUXF5_13_16_2: MUXF5
      port map (
        O  => WB_Fwd_II,           -- [out std_logic]
        I0 => WB_Fwd_I3,           -- [in  std_logic]
        I1 => WB_Fwd_I4,           -- [in  std_logic]
        S  => Select_Bits(2)       -- [in  std_logic]
      );
      
      WB_Fwd <= ( (     WB_Exception_Taken ) and ( WB_PC                 ) ) or
                ( ( not WB_Exception_Taken ) and ( WB_Fwd_I or WB_Fwd_II ) );
      
    end generate Using_WB_13_16_Size;
    
    ----------------------------------------
    -- WB mux with other number of inputs
    ----------------------------------------
    Using_WB_Other_Size: if( Data_Bits'length > 16 ) generate
    begin
      WB_Fwd <= ( (     WB_Exception_Taken ) and WB_PC                ) or
                ( ( not WB_Exception_Taken ) and Vector_OR(Data_Bits) );
  
    end generate Using_WB_Other_Size;
  end generate Using_LUT4_Based;

end architecture IMP;