wb_mux_bit_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: wb_mux_bit_gti.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- wb_mux_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc. 
-- **
-- ** Unmodified source code is guaranteed to place and route, 
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: wb_mux_bit_gti.vhd
-- Version: v1.00a
-- Description: Write Back stage main mux (per bit)
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              wb_mux_gti.vhd
--                wb_mux_bit_gti.vhd
-------------------------------------------------------------------------------
-- Author:          rikardw
-- History:
--   rikardw  2006-09-01    - First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY_>I_<#|FUNC>" , "ENTITY>_I#" 
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                      -- instruction fetch
--    OF                      -- operand fetch
--    EX                      -- execute
--    MEM                     -- memory
--    WB                      -- write back
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;


library unisim;
use unisim.vcomponents.all;


-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity WB_Mux_Bit is
  generic(
    C_TARGET            : TARGET_FAMILY_TYPE := VIRTEX4;
    C_LUT_SIZE          : natural := 4;
    C_DATA_WIDTH        : natural := 5
  );  
  port(
    Select_Bits         : in  std_logic_vector(0 to (C_DATA_WIDTH - 1) / C_LUT_SIZE);
    Data_Bits           : in  std_logic_vector(0 to C_DATA_WIDTH - 1);
  
    WB_Exception_Taken  : in  std_logic; -- taking an exception
    WB_PC               : in  std_logic;

    WB_Fwd              : out std_logic  -- Write back forwarding data
  );
end entity WB_Mux_Bit;

--------------------------------------------------------------------------
-- Architecture section
--------------------------------------------------------------------------

architecture IMP of WB_Mux_Bit is
  
  -- Constants to determine the architecture that shall be used to 
  -- implement the vectorized OR logic.
  constant USE_LUT6_BASED   : boolean:= (C_TARGET = VIRTEX5);
  
  -- Generic vector OR function.
  function Vector_OR(data : std_logic_vector) 
  return std_logic is
    variable tmp : std_logic:= '0';
  begin
    for I in data'range loop
      tmp := tmp or data(I);
    end loop;
    
    return tmp;
  end function Vector_OR;
  
  component MUXF5 is
    port (
      O : out std_logic;
      I0 : in std_logic;
      I1 : in std_logic;
      S : in std_logic
    );
  end component MUXF5;
  
  component MUXF6 is
    port (
      O : out std_logic;
      I0 : in std_logic;
      I1 : in std_logic;
      S : in std_logic
    );
  end component MUXF6;
  
begin

  -- -------------------------------------------------------------------------
  -- USE LUT6 BASED ARCHITECTURES
  -- -------------------------------------------------------------------------
  Using_LUT6_Based: if( USE_LUT6_BASED ) generate
  begin
    ----------------------------------------
    -- WB mux with 1-4 inputs
    ----------------------------------------
    Using_WB6_1_4_Size: if( Data_Bits'length >= 1 and Data_Bits'length <= 4 ) generate
    begin
      -- Implemented as 1 LUT.
      -- => 1 logic level.
      --
      WB_Fwd <= ( (     WB_Exception_Taken ) and WB_PC                ) or
                ( ( not WB_Exception_Taken ) and Vector_OR(Data_Bits) );
  
    end generate Using_WB6_1_4_Size;
  
    ----------------------------------------
    -- WB mux with 5-6 inputs
    ----------------------------------------
    Using_WB6_5_6_Size: if( Data_Bits'length >= 5 and Data_Bits'length <= 6 ) generate
      
      signal WB_Fwd_I1  : std_logic;
      
    begin
      -- Implemented as 1 LUT -> 1 MUX.
      -- => 1 logic level.
      --
      WB_Fwd_I1 <= Vector_OR(Data_Bits);
      
      -- Infere F7(A/B)MUX in Virtex5.
      WB_Fwd    <= WB_PC when (WB_Exception_Taken = '1') else WB_Fwd_I1;
      
    end generate Using_WB6_5_6_Size;
  
    ----------------------------------------
    -- WB mux with 7-9 inputs
    ----------------------------------------
    Using_WB6_7_9_Size: if( Data_Bits'length >= 7 and Data_Bits'length <= 9 ) generate
      
      signal WB_Fwd_I   : std_logic;
      
    begin
      -- Implemented as 1 LUT -> 1 LUT.
      -- => 2 logic levels.
      --
      WB_Fwd_I <= Vector_OR(Data_Bits(0 to 5));
      WB_Fwd <= ( (     WB_Exception_Taken ) and ( WB_PC                                                  ) ) or
                ( ( not WB_Exception_Taken ) and ( WB_Fwd_I or Vector_OR(Data_Bits(6 to Data_Bits'right)) ) );
      
    end generate Using_WB6_7_9_Size;

    ----------------------------------------
    -- WB mux with 10-14 inputs
    ----------------------------------------
    Using_WB6_10_14_Size: if( Data_Bits'length >= 10 and Data_Bits'length <= 14 ) generate
      
      signal WB_Fwd_I1  : std_logic;
      signal WB_Fwd_I2  : std_logic;
      
    begin
      -- Implemented as 2 LUT -> 1 LUT.
      -- => 2 logic levels.
      --
      WB_Fwd_I1 <= Vector_OR(Data_Bits(0 to 5));
      WB_Fwd_I2 <= Vector_OR(Data_Bits(8 to Data_Bits'right));
      
      WB_Fwd <= ( (     WB_Exception_Taken ) and ( WB_PC                        ) ) or