operand_select_bit.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: operand_select_bit.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- Operand Select Bit - entity/achitecture
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        operand_select_bit.vhd
-- Version:         v1.00a
-- Description:     One bit of operand select mux
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              operand_select_bit.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;


library Unisim;
use Unisim.vcomponents.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity Operand_Select_Bit is
  generic (
    -- Size generics
    C_TARGET             : TARGET_FAMILY_TYPE;
    C_EXCEPTION_ADDR_BIT : std_logic := '0';
    C_INTERRUPT_ADDR_BIT : std_logic := '0';
    C_EXT_BRK_ADDR_BIT   : std_logic := '0';
    C_ONLY_PC            : boolean   := false;
    C_DEBUG_ENABLED      : integer   := 0;
    C_LOWER_HALFWORD     : boolean   := true;
    C_LSB_BIT            : boolean   := true
    );
  port (
    Clk   : in std_logic;
    Reset : in boolean;

    OF_PipeRun : in boolean;

    Reg1_Data    : in std_logic;
    EX_Result    : in std_logic;
    Res_Forward1 : in boolean;

    PC_OF      : in std_logic;
    Enable_MSR : in std_logic;
    MSR        : in std_logic;
    OpSel1_PC  : in boolean;

    OpSel1_SPR : in boolean;

    Reg2_Data    : in std_logic;
    Res_Forward2 : in boolean;

    Sign_Imm    : in std_logic;
    Imm_Reg     : in std_logic;
    Use_Imm_Reg : in boolean;

    OpSel2_Imm     : in boolean;
    Take_Exception : in boolean;
    Take_Interrupt : in boolean;
    Take_Ext_BRK   : in boolean;
    Exception_or_BRK : in boolean;
    Store_PC_For_Intr      : in boolean;
    Store_PC_For_Intr_NoImm: in boolean;

    Reg1  : out std_logic;
    Op1   : out std_logic;
    Op2   : out std_logic;
    Op2_C : out std_logic
    );

end entity Operand_Select_Bit;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of Operand_Select_Bit is

  signal run_Pipe         : std_logic;
  signal take_Interrupt_I : std_logic;
  signal take_Exception_I : std_logic;
  signal Store_PC_For_Intr_S      : std_logic;
  signal Store_PC_For_Intr_NoImm_S: std_logic;

  signal sel_Forward1     : std_logic;
  signal sel_Forward2     : std_logic;
  signal opSel1_PC_I      : std_logic;
  signal opSel1_SPR_I     : std_logic;

  signal opSel2_Imm_I     : std_logic;

  signal op1_Reg : std_logic;
  signal op1_SPR : std_logic;
  signal op1_I   : std_logic;

  signal op2_Reg : std_logic;
  signal op2_Imm : std_logic;
  signal op2_I   : std_logic;

  signal op2_II : std_logic;

  signal exception_or_brk_I : std_logic;

  -----------------------------------------------------------------------------
  -- Function to get the INIT value for the vector address LUT3
  -----------------------------------------------------------------------------
  function Calc_Vec_Init_Str (Brk_Addr : std_logic; Exc_Addr : std_logic) return string is
    variable temp : std_logic_vector(0 to 1) := Brk_Addr & Exc_Addr;
  begin  -- function Calc_Vec_Init_Str
    case temp is
      when "00"   => return "10";
      when "01"   => return "BA";
      when "10"   => return "54";
      when "11"   => return "FE";
      when others => return "10";
    end case;
  end function Calc_Vec_Init_Str;

  function Calc_Vec_Init_bit (Brk_Addr : std_logic; Exc_Addr : std_logic) return bit_vector is
    variable temp : std_logic_vector(0 to 1) := Brk_Addr & Exc_Addr;
  begin  -- function Calc_Vec_Init_bit
    case temp is
      when "00"   => return X"10";
      when "01"   => return X"BA";
      when "10"   => return X"54";
      when "11"   => return X"FE";
      when others => return X"10";
    end case;
  end function Calc_Vec_Init_bit;

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------

begin  -- architecture IMP

  -- rst           <= '1' when Reset        else '0';
  run_Pipe     <= '1' when OF_PipeRun   else '0';
  sel_Forward1 <= '1' when Res_Forward1 else '0';
  sel_Forward2 <= '1' when Res_Forward2 else '0';
  opSel1_PC_I  <= '1' when OpSel1_PC    else '0';
  opSel1_SPR_I <= '1' when OpSel1_SPR   else '0';
  opSel2_Imm_I <= '1' when OpSel2_Imm   else '0';

  take_Interrupt_I <= '1' when Take_Interrupt else '0';
  take_Exception_I <= '1' when Take_Exception else '0';
  -- take_Ext_Brk_I   <= '1' when Take_Ext_BRK   else '0';
  Store_PC_For_Intr_S       <= '1' when Store_PC_For_Intr       else '0';
  Store_PC_For_Intr_NoImm_S <= '1' when Store_PC_For_Intr_NoImm else '0';

  exception_or_brk_I <= '1' when Exception_or_BRK else '0';
  
  -----------------------------------------------------------------------------
  -- Select Op1
  -----------------------------------------------------------------------------
  Op1_Mux2_1 : LUT3                     -- Init Value for a Mux is 00CA
    generic map(
      INIT => X"CA"
      )
    port map (
      O  => op1_Reg,                    -- [out]
      I0 => Reg1_Data,                  -- [in]
      I1 => EX_Result,                  -- [in]
      I2 => sel_Forward1);              -- [in]

  Only_PC : if (C_ONLY_PC) generate
    Op1_Mux2_2 : LUT2
      generic map (
        INIT => "1000")                 -- [bit_vector]
      port map (
        O  => op1_SPR,                  -- [out std_logic]
        I0 => PC_OF,                    -- [in std_logic]
        I1 => opSel1_PC_I);             -- [in std_logic]
  end generate Only_PC;

  Both_PC_and_MSR : if (not C_ONLY_PC) generate
    Op1_Mux2_2 : LUT4                   -- Init Value for a Mux is 00CA
      generic map(
        INIT => X"CAC0"
        )
      port map (
        O  => op1_SPR,                  -- [out]
        I0 => MSR,                      -- [in]
        I1 => PC_OF,                    -- [in]
        I2 => opSel1_PC_I,              -- [in]
        I3 => Enable_MSR);              -- [in]
  end generate Both_PC_and_MSR;

  Op1_MUXF5 : MUXF5
    port map (
      I0 => op1_Reg,                    -- [in]
      I1 => op1_SPR,                    -- [in]
      S  => opSel1_SPR_I,               -- [in]
      O  => op1_I);                     -- [out]

  Op1_DFF : FDE
    port map (
      Q  => Op1,                        -- [out]
      D  => op1_I,                      -- [in]
      C  => Clk,                        -- [in]
      CE => run_Pipe);                  -- [in]

  Op1_Reg_DFF : FDE
    port map (
      Q  => Reg1,                       -- [out]
      D  => op1_Reg,                    -- [in]
      C  => Clk,                        -- [in]
      CE => run_Pipe);                  -- [in]

  -----------------------------------------------------------------------------
  -- Selection of Op2
  -----------------------------------------------------------------------------
  -- The Mux can be instanciated in with two different INIT values dependent on
  -- the value of the generic Instruction_Addr_Bit
  --
  -- Function
  -- if Take_Interrupt is false then it is just a mux between Reg2_Data and Prev_Result
  -- if Take_Interrupt is true the value of Interrupt_Addr_Bit is force as the
  -- result
  --                  Karnough map
  --
  --             bit 1,0
  --  bit 3,2   Prev_Result,Reg2_Data
  --  Take_Intr, Sel_Fwd2  00  01  11  10 
  --               00       0   1   1   0  1010
  --               01       0   0   1   1  1100
  --               11       A   A   A   A  AAAA 
  --               10       A   A   A   A  AAAA
  -- Where A is the value of the generic Interrupt_Addr_Bit
  -- Init String (when A = '0') = 0000 0000 1100 1010 = 00CA
  -- Init String (when A = '1') = 1111 1111 1100 1010 = FFCA
  ---------------------------------------------------------------------------

  Intr_Addr_bit_is_0 : if C_INTERRUPT_ADDR_BIT = '0' generate
    Op2_Mux2_1 : LUT4
      generic map(
        INIT => X"00CA"
        )
      port map (
        O  => op2_Reg,                  -- [out]
        I0 => Reg2_Data,                -- [in]
        I1 => EX_Result,                -- [in]
        I2 => sel_Forward2,             -- [in]
        I3 => take_Interrupt_I);        -- [in]
  end generate Intr_Addr_bit_is_0;

  Intr_Addr_bit_is_1 : if C_INTERRUPT_ADDR_BIT = '1' generate
    Op2_Mux2_1 : LUT4
      generic map(
        INIT => X"FFCA"
        )
      port map (
        O  => op2_Reg,                  -- [out]
        I0 => Reg2_Data,                -- [in]
        I1 => EX_Result,                -- [in]
        I2 => sel_Forward2,             -- [in]
        I3 => take_Interrupt_I);        -- [in]
  end generate Intr_Addr_bit_is_1;

  -----------------------------------------------------------------------------
  -- The same as for Op2_Mux2_1 but with Take_Exception and Exception_Addr_Bit
  -----------------------------------------------------------------------------

  -- If it's a bit in the lower halfword (16..31) than the Sign_Imm and Imm_Reg
  -- is the same value. We will use that for muxing in the exception or ext_brk
  -- vector addresses
  Lower_Part : if (C_LOWER_HALFWORD) generate
    signal take_Ext_Brk_I : std_logic;
  begin
    take_Ext_Brk_I <= '1' when Take_Ext_BRK else '0';

    Op2_Mux2_2 : LUT3
      generic map(
        INIT => Calc_Vec_Init_bit(C_EXT_BRK_ADDR_BIT, C_EXCEPTION_ADDR_BIT)
        )
      port map (
        O  => op2_Imm,                  -- [out]
        I0 => take_Exception_I,         -- [in]
        I1 => take_Ext_Brk_I,           -- [in]
        I2 => Imm_Reg);                 -- [in]
  end generate Lower_Part;

  Upper_Part : if (not(C_LOWER_HALFWORD)) generate
    signal use_Imm_Reg_I : std_logic;
  begin
    use_Imm_Reg_I <= '1' when Use_Imm_Reg else '0';

    -- Doesn't matter which addr bit we choose. The MSB 16 bits has to be the same
    Exc_Addr_Bit_Is_0 : if C_EXCEPTION_ADDR_BIT = '0' generate
      Op2_Mux2_2 : LUT4
        generic map(
          INIT => X"00CA"
          )
        port map (
          O  => op2_Imm,                -- [out]
          I0 => Sign_Imm,               -- [in]
          I1 => Imm_Reg,                -- [in]
          I2 => use_Imm_Reg_I,          -- [in]
          I3 => exception_or_brk_I);    -- [in]
    end generate Exc_Addr_Bit_Is_0;

    Exc_Addr_Bit_Is_1 : if C_EXCEPTION_ADDR_BIT = '1' generate
      Op2_Mux2_2 : LUT4
        generic map(
          INIT => X"FFCA"
          )
        port map (
          O  => Op2_Imm,                -- [out]
          I0 => Sign_Imm,               -- [in]
          I1 => Imm_Reg,                -- [in]
          I2 => use_Imm_Reg_I,          -- [in]
          I3 => exception_or_brk_I);    -- [in]
    end generate Exc_Addr_Bit_Is_1;

  end generate Upper_Part;


  Op2_MUXF5 : MUXF5
    port map (
      I0 => op2_Reg,                    -- [in]
      I1 => op2_Imm,                    -- [in]
      S  => opSel2_Imm_I,               -- [in]
      O  => op2_I);                     -- [out]

  LSB_DFF : if (C_LSB_BIT) generate
  begin
    Op2_DFF : FDRE
      port map (
        Q  => Op2_II,                     -- [out std_logic]
        C  => Clk,                        -- [in  std_logic]
        CE => run_Pipe,                   -- [in  std_logic]
        D  => op2_I,                      -- [in  std_logic]
        R  => Store_PC_For_Intr_S);       -- [in  std_logic]
  end generate LSB_DFF;
      
  MSB_DFF : if (not C_LSB_BIT) generate
  begin
    Op2_DFF : FDRSE
      port map (
        Q  => Op2_II,                     -- [out std_logic]
        C  => Clk,                        -- [in  std_logic]
        CE => run_Pipe,                   -- [in  std_logic]
        D  => op2_I,                      -- [in  std_logic]
        R  => Store_PC_For_Intr_NoImm_S,  -- [in  std_logic]
        S  => Store_PC_For_Intr_S);       -- [in  std_logic]
  end generate MSB_DFF;
      
  Op2   <= Op2_II;
  Op2_C <= Op2_II;

end architecture IMP;