mmu_utlb.vhd

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-------------------------------------------------------------------------------
-- $Id: mmu_utlb.vhd,v 1.2 2007/10/23 11:00:32 stefana Exp $
-------------------------------------------------------------------------------
-- mmu_utlb.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2007 by Xilinx, Inc. All rights reserved.               **
--  **                                                                       **
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--  **  information of Xilinx, Inc. , is distributed by                      **
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--  **                                                                       **
--  **  Unmodified source code is guaranteed to place and route,             **
--  **  function and run at speed according to the datasheet                 **
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--  **  obligation on the part of Xilinx to provide support.                 **
--  **                                                                       **
--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
--  **                                                                       **
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--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        mmu_utlb.vhd
--
-- Description:     This file contains an implementation of the unified Memory
--                  Management Unit Translation Look-aside Buffer, using block
--                  RAM to emulate a fully associative memory.
--
-- VHDL-Standard:   VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:   
--              mmu_utlb.vhd
--                mmu_utlb_ram.vhd
--
-------------------------------------------------------------------------------
-- Author:          stefana
-- Revision:        $Revision: 1.2 $
-- Date:            $Date: 2007/10/23 11:00:32 $
--
-- History:
--   stefana 2006-10-27    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

-- pragma xilinx_rtl_off
library unisim;
use unisim.vcomponents.all;
-- pragma xilinx_rtl_on
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;
use Microblaze_v7_10_a.MMU_Types.all;

entity MMU_UTLB is
  generic (
    C_TARGET        : TARGET_FAMILY_TYPE;
    C_MMU_TLB_WRITE : boolean := true
  );
  port (
    Clk           : in  std_logic;
    Reset         : in  std_logic;

    IVAddr        : in  TAG_TYPE;
    IValid        : in  std_logic;
    IVMode        : in  std_logic;

    DVAddr        : in  TAG_TYPE;
    DValid        : in  std_logic;
    DVMode        : in  std_logic;

    PID           : in  TID_TYPE;

    RegAddr       : in  TLB_Index_Type;
    RegData       : in  DATA_TYPE;
    RegDataLowIn  : in  std_logic_vector(0 to 3);
    RegRdLo       : in  boolean;
    RegRdHi       : in  boolean;
    RegWrLo       : in  std_logic;
    RegWrHi       : in  std_logic;
    RegWrSx       : in  std_logic;

    SizeMask      : out SIZE_Addr_Type;
    MaskedData    : out TLBHI_Type;
    DataHigh      : out TLBHI_Type;
    DataLow       : out DATA_TYPE;
    RegDataLowOut : out std_logic_vector(0 to 3);

    IDataBusy     : out std_logic;
    DDataBusy     : out std_logic;
    RDataBusy     : out std_logic;
    IDataRdy      : out std_logic;
    DDataRdy      : out std_logic;
    RDataRdy      : out std_logic;
    Hit           : out std_logic;
    HitIndex      : out TLB_INDEX_Type;

    EX_MMU_Stall  : out boolean
  );
end entity MMU_UTLB;

library IEEE;
use IEEE.numeric_std.all;

architecture IMP of MMU_UTLB is

  component MMU_UTLB_RAM
    port(
      clka  : in std_logic;
      clkb  : in std_logic;
      ena   : in std_logic;
      enb   : in std_logic;
      wea   : in std_logic;
      web   : in std_logic;
      addra : in std_logic_vector(8 downto 0);
      addrb : in std_logic_vector(8 downto 0);
      dia   : in std_logic_vector(35 downto 0);
      dib   : in std_logic_vector(35 downto 0);
      doa   : out std_logic_vector(35 downto 0);
      dob   : out std_logic_vector(35 downto 0)
    );
  end component MMU_UTLB_RAM;

  component carry_compare is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE;
      Size     : natural);
    port (
      A_Vec     : in  std_logic_vector(0 to Size-1);
      B_Vec     : in  std_logic_vector(0 to Size-1);
      Carry_In  : in  std_logic;
      Carry_Out : out std_logic);
  end component carry_compare;
  
  component carry_compare_mask is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE;
      Size     : natural);
    port (
      A_Vec     : in  std_logic_vector(0 to Size-1);
      B_Vec     : in  std_logic_vector(0 to Size-1);
      Mask      : in  std_logic_vector(0 to Size-1);
      Carry_In  : in  std_logic;
      Carry_Out : out std_logic);
  end component carry_compare_mask;

  component carry_and is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE);
    port (
      Carry_IN  : in  std_logic;
      A         : in  std_logic;
      Carry_OUT : out std_logic);
  end component carry_and;
  
  subtype DirectA_Bits is std_logic_vector(12 to 19);  -- TBD
  subtype DirectB_Bits is std_logic_vector(5  to 11);  -- TBD

  subtype TID_Type is std_logic_vector(28 to 35);

  type State_Type is (DirectCompare, Search, SearchStart,
                      Found, FoundDone, NotFound, WriteHICheck,
                      WriteHI, WriteHIDirectA, WriteHIInvalA,
                      WriteHIInvalB, WriteHIDirectB, WriteLO,
                      ReadHI, ReadLO);

  type Access_Type is (AccessNone, AccessData, AccessInstr, AccessReg);

  constant C_TID_0 : integer := 26; -- Use TLBHI.E bit as TID0

  -- Signals
  signal VAddr         : TAG_Type;

  signal AddrA         : std_logic_vector(0 to 8);
  signal AddrB         : std_logic_vector(0 to 8);

  signal DataInA       : TLBHI_Type;
  signal DataInB       : TLBHI_Type;

  signal DataOutA      : TLBHI_Type;
  signal DataOutB      : TLBHI_Type;

  signal ENA           : std_logic;
  signal ENB           : std_logic;
  signal WEA           : std_logic;
  signal WEB           : std_logic;

  signal InputCmp          : TAG_Type;
  signal SizeMaskA         : SIZE_Addr_Type;
  signal TagCmpA           : TAG_Type;
  signal pidA_mask         : TID_TYPE;
  signal equalA_tag1_part1 : std_logic;
  signal equalA_tag1       : std_logic;
  signal equalA_tag3       : std_logic;
  signal equalA_pid        : std_logic;
  signal Hit_SearchA_S     : std_logic;
  signal Hit_DirectA_S     : std_logic;
  signal Hit_SearchA       : boolean;
  signal Hit_DirectA       : boolean;

  signal SizeMaskB         : SIZE_Addr_Type;
  signal EqualB_TAG1       : std_logic;
  signal EqualB_TAG2_part1 : std_logic;
  signal EqualB_TAG2       : std_logic;
  signal EqualB_TAG3       : std_logic;
  signal pidB_mask         : TID_TYPE;
  signal EqualB_PID        : std_logic;
  signal Hit_SearchB_S     : std_logic;
  signal Hit_DirectB_S     : std_logic;
  signal Hit_SearchB       : boolean;
  signal Hit_DirectB       : boolean;

  signal AddrSel       : std_logic_vector(0 to 2);

  signal Counter       : TLB_Index_Type;

  signal Index         : TLB_Index_Type;
  signal IndexA        : TLB_Index_Type;
  signal IndexB        : TLB_Index_Type;

  signal TagA          : std_logic_vector(0 to 7);
  signal TagB          : std_logic_vector(0 to 6);

  signal TagInvalA     : std_logic_vector(0 to 7);
  signal TagInvalB     : std_logic_vector(0 to 6);

  signal IValid_Active : std_logic;
  signal IValid_Keep   : std_logic;
  signal Load          : boolean;
  signal Count         : boolean;
  signal CountCarry    : boolean;
  signal FoundNx       : boolean;
  signal NotFoundNx    : boolean;
  signal AccessKind    : Access_Type;

  signal State         : State_Type;

begin  -- architecture IMP

  VAddr <= IVAddr when DValid = '0' else
           DVAddr;

  -- Clock virtual address for comparison
  VAddr_DFF: process (Clk)
  begin
    if Clk'event and Clk = '1' then
      if AccessKind = AccessReg or RegWrSx = '1' then
        InputCmp <= RegData(InputCmp'range);
      elsif AccessKind = AccessNone then
        InputCmp <= VAddr;
      end if;
    end if;
  end process VAddr_DFF;

  -- Assign block RAM inputs
  AddrA <= '0'    & VAddr(DirectA_Bits'range) when AddrSel = "000" else  -- Rd
           "110"  & Counter(1 to 5) & '0'     when AddrSel = "001" else  -- Rd
           "110"  & Index                     when AddrSel = "011" else  -- Rd
           '0'    & TagA                      when AddrSel = "100" else  -- Wr
           "10"   & TagB                      when AddrSel = "101" else  -- Wr
           '0'    & TagInvalA                 when AddrSel = "110" else  -- Wr
           "10"   & TagInvalB                 when AddrSel = "010" else  -- Wr
           "110"  & RegAddr; -- Rd/Wr

  AddrB <= "10"   & VAddr(DirectB_Bits'range) when AddrSel = "000" else  -- Rd
           "110"  & Counter(1 to 5) & '1'     when AddrSel = "001" else  -- Rd
           "111"  & Index                     when AddrSel = "011" else  -- Rd
           "111"  & RegAddr; -- Rd/Wr

  AssignDataInA: process (PID, RegAddr, RegData, AddrSel)
  begin
    DataInA <= RegData(0 to 27) & PID;
    if AddrSel = "100" then
      DataInA(DirectA_Bits'left to DirectA_Bits'left + 5) <= RegAddr;
    end if;
    if AddrSel = "101" then
      DataInA(DirectB_Bits'left to DirectB_Bits'left + 5) <= RegAddr;
    end if;
    if AddrSel = "110" or AddrSel = "010" then
      DataInA(C_VALID) <= '0';
    end if;
    -- Set the TID_0 bit if PID is not 0
    if PID = (PID'range => '0') then
      DataInA (C_TID_0) <= '0';
    else
      DataInA (C_TID_0) <= '1';
    end if;
  end process AssignDataInA;

  DataInB <= RegData & RegDataLowIn;

  ENA <= '1' when IVMode = '1' or DVMode = '1' or WEA = '1' or
                  State /= DirectCompare or RegRdHi else '0';
  ENB <= '1' when IVMode = '1' or DVMode = '1' or WEB = '1' or
                  State /= DirectCompare or RegRdLo else '0';

  -- Block RAM implementation
  MMU_UTLB_RAM_I : MMU_UTLB_RAM
    port map (
      clka  => Clk,
      clkb  => Clk,
      ena   => ENA,
      enb   => ENB,
      wea   => WEA,
      web   => WEB,
      addra => AddrA,
      addrb => AddrB,
      dia   => DataInA,
      dib   => DataInB,
      doa   => DataOutA,
      dob   => DataOutB
    );

  -- Comparison of block RAM outputs
  SizeMaskA   <= C_SIZE_MASK(to_integer(unsigned(DataOutA(SIZE_Type'range))));
  TagCmpA     <= DataOutA(TAG_MSB_Type'range) &
                 (DataOutA(TAG_LSB_Type'range) and SizeMaskA);

  -----------------------------------------------------------------------------
  -- EqualA_TAG1
  -- InputCmpA   <= InputCmp(TAG_MSB_Type'range) &
  --                (InputCmp(TAG_LSB_Type'range) and SizeMaskA);
  -- EqualA_TAG1 <= TagCmpA(TagCmpA'left to DirectA_Bits'left - 1) =
  --                InputCmpA(InputCmpA'left to DirectA_Bits'left - 1);
  -----------------------------------------------------------------------------
  eqa1_carry_compare : carry_compare
    generic map (
      C_TARGET => C_TARGET,
      Size     => TAG_MSB_Type'Length)
    port map (
      A_Vec     => InputCmp(TAG_MSB_Type'range),
      B_Vec     => DataOutA(TAG_MSB_Type'range),
      Carry_In  => '1',
      Carry_Out => equalA_tag1_part1);

  eqa1_carry_compare_mask: carry_compare_mask
    generic map (
      C_TARGET => C_TARGET,
      Size     => DirectA_Bits'left - TAG_MSB_Type'right - 1)
    port map (
      A_Vec     => InputCmp(TAG_MSB_Type'right+1 to DirectA_Bits'left-1),
      B_Vec     => DataOutA(TAG_MSB_Type'right+1 to DirectA_Bits'left-1),
      Mask      => SizeMaskA(TAG_MSB_Type'right+1 to DirectA_Bits'left-1),
      Carry_In  => equalA_tag1_part1,
      Carry_Out => equalA_tag1);

  -----------------------------------------------------------------------------
  -- EqualA_TAG3
  -- EqualA_TAG3 <= TagCmpA(DirectA_Bits'right + 1 to InputCmpA'right) =
  --                InputCmpA(DirectA_Bits'right + 1 to InputCmpA'right);
  -----------------------------------------------------------------------------
  eqa3_carry_compare_mask_I1: carry_compare_mask
    generic map (
      C_TARGET => C_TARGET,
      Size     => TAG_Type'right - DirectA_Bits'right)
    port map (
      A_Vec     => InputCmp(DirectA_Bits'right+1 to TAG_Type'right),
      B_Vec     => DataOutA(DirectA_Bits'right+1 to TAG_Type'right),
      Mask      => SizeMaskA(DirectA_Bits'right+1 to TAG_Type'right),
      Carry_In  => equalA_tag1,
      Carry_Out => equalA_tag3);

  -----------------------------------------------------------------------------
  -- EqualA_PID
  -- EqualA_PID  <= DataOutA(TID_Type'range) = PID or
  --                DataOutA(TID_Type'range) = (TID_Type'range => '0');
  -----------------------------------------------------------------------------
  pidA_mask <= (others => DataOutA(C_TID_0));

  eqapid_carry_compare_mask_I1 : carry_compare_mask
    generic map (
      C_TARGET  => C_TARGET,
      Size      => 8)