instr_mux.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: instr_mux.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- instr_mux.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
--  **                                                                       **
--  **  This text contains proprietary, confidential                         **
--  **  information of Xilinx, Inc. , is distributed by                      **
--  **  under license from Xilinx, Inc., and may be used,                    **
--  **  copied and/or disclosed only pursuant to the terms                   **
--  **  of a valid license agreement with Xilinx, Inc.                       **
--  **                                                                       **
--  **  Unmodified source code is guaranteed to place and route,             **
--  **  function and run at speed according to the datasheet                 **
--  **  specification. Source code is provided "as-is", with no              **
--  **  obligation on the part of Xilinx to provide support.                 **
--  **                                                                       **
--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
--  **                                                                       **
--  **  The Xilinx Support Hotline does not have access to source            **
--  **  code and therefore cannot answer specific questions related          **
--  **  to source HDL. The Xilinx Support Hotline will only be able          **
--  **  to confirm the problem in the Netlist version of the core.           **
--  **                                                                       **
--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        instr_mux.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              instr_mux.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2004-10-08    First Version
--   rikard 2006-08-30    Merged with GTi
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

library microblaze_v7_10_a;
use microblaze_v7_10_a.microblaze_types.all;

entity instr_mux is
  generic (
    C_USE_I_EXT        :     boolean;
    C_USE_ICACHE       :     boolean;
    C_DEBUG_ENABLED    :     boolean;
    C_USE_I_LMB        :     boolean
    );
  port (
    ILMB_data          : in  DATA_TYPE;
    ILMB_data_strobe   : in  std_logic;
    IEXT_data          : in  DATA_TYPE;
    IEXT_data_strobe   : in  std_logic;
    ICache_data        : in  DATA_TYPE;
    IDebug_data        : in  DATA_TYPE;
    IDebug_data_strobe : in  std_logic;
    IB_data            : out DATA_TYPE
    );
end entity instr_mux;

library Unisim;
use Unisim.vcomponents.all;

architecture IMP of instr_mux is

  component MUXF5 is
     port (
       O : out std_logic;
       I0 : in std_logic;
       I1 : in std_logic;
       S : in std_logic
     );
   end component MUXF5;

  signal muxA     : DATA_TYPE;
  signal muxB     : DATA_TYPE;
  signal sel_muxb : std_logic;

begin  -- architecture IMP

  -------------------------------------------------------------------------------
  -- Handling of IReady is done outside this module
  -------------------------------------------------------------------------------

  -----------------------------------------------------------------------------
  -- Building a maximum 4-1 mux of the different source of new instructions
  -----------------------------------------------------------------------------

  -----------------------------------------------------------------------------
  -- First mux
  -----------------------------------------------------------------------------
  -- Both IEXT and ICache
  EXT_and_Cache : if (C_USE_ICACHE and C_USE_I_EXT) generate
    muxA <= IEXT_data when IEXT_data_strobe = '1' else ICache_data;
  end generate EXT_and_Cache;

  -- Only EXT
  EXT_and_No_Cache : if (C_USE_I_EXT and not C_USE_ICACHE) generate
    muxA <= IEXT_data;
  end generate EXT_and_No_Cache;

  -- Only Cache
  No_EXT_but_Cache : if (not C_USE_I_EXT and C_USE_ICACHE) generate
    muxA <= ICache_data;
  end generate No_EXT_but_Cache;

  -- No Cache or EXT
  No_Cache_and_No_EXT : if (not C_USE_I_EXT and not C_USE_ICACHE) generate
    muxA     <= muxB;
  end generate No_Cache_and_No_EXT;
  -----------------------------------------------------------------------------
  -- Second mux
  -----------------------------------------------------------------------------
  --Both LMB and Debug
  LMB_and_Debug       : if (C_USE_I_LMB and C_DEBUG_ENABLED) generate
    muxB     <= IDebug_data when IDebug_data_strobe = '1' else ILMB_data;
    sel_muxb <= IDebug_data_strobe or ILMB_data_strobe;
  end generate LMB_and_Debug;

  -- Only LMB
  LMB_and_no_Debug : if (C_USE_I_LMB and not C_DEBUG_ENABLED) generate
    muxB     <= ILMB_data;
    sel_muxb <= ILMB_data_strobe;
  end generate LMB_and_no_Debug;

  -- Only Debug
  No_LMB_but_Debug : if (not C_USE_I_LMB and C_DEBUG_ENABLED) generate
    muxB     <= IDebug_data;
    sel_muxb <= IDebug_data_strobe;
  end generate No_LMB_but_Debug;

  -- Neither debug or LMB
  No_LMB_and_No_Debug : if (not C_USE_I_LMB and not C_DEBUG_ENABLED) generate
    muxB     <= muxA;
    sel_muxb <= '0';
  end generate No_LMB_and_No_Debug;
  
  -----------------------------------------------------------------------------
  -- The Last MUX
  -----------------------------------------------------------------------------
  
  Full_Last_Mux: if( (   C_USE_I_EXT and C_USE_ICACHE   and ( C_USE_I_LMB or  C_DEBUG_ENABLED ) ) or 
                     ( ( C_USE_I_EXT                  ) and   C_USE_I_LMB and C_DEBUG_ENABLED   ) ) generate
  begin
    -- All is selected, use MUXF5 for efficient selection.
  
    The_Mux : for I in IB_data'range generate
    begin
      MUXF5_I1 : MUXF5
        port map (
          O  => IB_data(I),             -- [out std_logic]
          I0 => muxA(I),                -- [in  std_logic]
          I1 => muxB(I),                -- [in  std_logic]
          S  => sel_muxb                -- [in  std_logic]
        );
    end generate The_Mux;
  
  end generate Full_Last_Mux;
  
  Not_Full_Last_Mux: if not ( (   C_USE_I_EXT and C_USE_ICACHE   and ( C_USE_I_LMB or  C_DEBUG_ENABLED ) ) or 
                              ( ( C_USE_I_EXT                  ) and   C_USE_I_LMB and C_DEBUG_ENABLED   ) ) generate
  begin
    IB_data    <= muxB when sel_muxb = '1' else muxA;
    
  end generate Not_Full_Last_Mux;
  
end architecture IMP;