decode_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

  signal ex_branch_with_delayslot : boolean;

  signal ex_msrset_i          : std_logic;
  signal ex_msrclr_i          : std_logic;
  signal ex_mfsmsr_i          : boolean;
  signal ex_MSR_set_decode    : std_logic;
  signal ex_MSR_clear_decode  : std_logic;
  signal ex_MSR_clear_vm_um_i : std_logic;
  signal ex_MSR_change_instr  : boolean;

  signal of_set_MSR_IE : boolean;
  signal of_set_MSR_IE_hold : boolean;

  -----------------------------------------------------------------------------
  -- Signal for BRK and RTBD
  -----------------------------------------------------------------------------
  signal of_clear_MSR_BIP : boolean;
  signal of_clear_MSR_BIP_hold : boolean;
  signal ex_set_bip            : boolean;
  
  -----------------------------------------------------------------------------
  -- Signals for FSL
  -----------------------------------------------------------------------------
  signal of_sel_fsl_i            : rboolean;
  signal of_fsl_put              : std_logic;
  signal of_fsl_get              : std_logic;
  signal of_fsl_test             : std_logic;
  signal of_fsl_control          : std_logic;
  signal of_fsl_blocking         : std_logic;
  signal of_fsl_exceptionable    : std_logic;
  signal of_fsl_atomic           : std_logic;
  signal ex_potential_exception  : boolean;
  signal mem_potential_exception : boolean;
  signal ex_sel_fsl_i            : rboolean;
  signal ex_fsl_stall            : rboolean;
  signal ex_fsl_put              : std_logic;
  signal ex_fsl_get              : std_logic;
  signal ex_fsl_test             : std_logic;
  signal ex_fsl_control          : std_logic;
  signal ex_fsl_blocking         : std_logic;
  signal ex_fsl_exceptionable    : std_logic;
  signal ex_fsl_atomic           : std_logic;
  signal mem_FSL_Ctrl_Error      : rboolean;
  signal FSL_Will_Break          : std_logic;
  signal FSL_Break               : std_logic;
  
  -----------------------------------------------------------------------------
  -- Signals for Exception detection
  -----------------------------------------------------------------------------

  signal of_set_MSR_EE : boolean;
  signal of_set_MSR_EE_hold : boolean;
  
  signal ex_fsl_break                      : boolean;
  signal ex_exception_no_load_store_mask   : boolean;
  signal ex_exception_no_load_store_unmask : boolean;
  signal ex_exception_no_load_store        : boolean;
  signal ex_exception_masked               : boolean;
  signal ex_exception_without_valid        : boolean;
  signal ex_exception                      : boolean;
  signal ex_exception_possible_branch      : boolean;
  signal ex_Exceptions_Enabled             : boolean;

  signal of_Illegal_Opcode     : rboolean;
  signal ex_Illegal_Opcode     : rboolean;

  signal ex_unalignment_exception : rboolean;

  signal ex_IExt_Exception : rboolean;  

  signal mem_clr_ESR            : boolean;
  signal mem_exception_i        : boolean;
  signal mem_exception_kind_i   : EXCEPTION_KIND_TYPE;
  signal mem_exception          : boolean;
  signal mem_exception_kind     : EXCEPTION_KIND_TYPE;
  signal mem_Exceptions_Enabled : boolean;

  signal wb_exception_i        : boolean;
  signal wb_exception          : boolean;
  signal wb_exception_kind_i   : EXCEPTION_KIND_TYPE;
  signal wb_exception_kind_ii  : EXCEPTION_KIND_TYPE;
  signal wb_intr_exception     : boolean;
  signal wb_hw_brk_exception   : boolean;
  signal wb_dbg_exception      : boolean;
  signal wb_common_exception   : boolean;

  signal ex_missed_fetch_on_branch_ended : boolean;

  signal ex_valid_and_no_exc_or_intr               : boolean;
  signal ex_valid_and_no_exc_or_intr_no_load_store : boolean;

  signal mem_wait_on_ready_N     : std_logic;
  signal mem_wait_on_ready_N_sel : std_logic;
  signal mem_PipeRun_sel         : std_logic;
  signal mem_PipeRun_Stdl        : std_logic;

  signal ex_Interrupt_Brk_combo   : boolean;
  signal ex_Instr_MMU_Excep_combo : boolean;

  -----------------------------------------------------------------------------
  -- Attributes
  -----------------------------------------------------------------------------
  attribute keep  : string;

  attribute keep of of_PipeRun_i        : signal is "true";
  attribute keep of of_PipeRun_Prefetch : signal is "true";
  attribute keep of ex_valid_jump       : signal is "true";

begin  -- architecture IMP

  reset_bool <= (reset = '1');

  flush_pipe <= reset_bool or wb_exception;
  
  --------------------------------------------------------------------------
  -- Component Instantiations
  --------------------------------------------------------------------------


  ex_PipeRun_dbg  <= ex_PipeRun_i and not wb_dbg_exception and not Dbg_freeze;
  mem_PipeRun_dbg <= mem_PipeRun_i and not wb_dbg_exception and not Dbg_freeze;
  
  PC_Module_I : PC_Module_gti
    generic map (
      C_TARGET => C_TARGET              -- [TARGET_FAMILY_TYPE]
      -- pragma xilinx_rtl_off
      ,
      C_U_SET  => C_U_SET               -- [string]
      -- pragma xilinx_rtl_on
      )
    port map (
      Clk   => Clk,                     -- [in  std_logic]
      Reset => Reset,                   -- [in  std_logic]

      IF_Valid_Fetch => if_valid_fetch_i,  -- [in  boolean]
      OF_PipeRun     => of_PipeRun_i,      -- [in  boolean]
      EX_PipeRun     => ex_PipeRun_dbg,      -- [in  boolean]
      MEM_PipeRun    => mem_PipeRun_dbg,     -- [in  boolean]

      IF_PC_Incr => if_pc_incr,         -- [in  boolean]

      EX_Jump       => ex_jump,         -- [in  boolean]
      EX_ALU_Result => EX_ALU_Result,   -- [in  DATA_TYPE]

      IF_PC_Write   => if_pc_write,     -- [in  boolean]
      IB_Buffer_En  => ib_buffer_en,    -- [in  slv_0to3]
      OF_Buffer_Sel => of_buffer_sel,   -- [in  slv_0to1]

      OF_PC   => OF_PC,                 -- [out DATA_TYPE]
      EX_PC   => EX_PC,                 -- [out DATA_TYPE]
      WB_PC   => WB_PC,                 -- [out DATA_TYPE]
      IB_Addr => IB_Addr                -- [out DATA_TYPE]
      );


  PreFetch_Buffer_I1 : PreFetch_Buffer_gti
    generic map (
      C_IEXT_BUS_EXCEPTION => C_IEXT_BUS_EXCEPTION,          -- [boolean]
      C_USE_MMU            => C_USE_MMU)                     -- [integer]
    port map (
      Clk                      => Clk,                       -- [in  std_logic]
      Reset                    => reset_bool,                -- [in  boolean]
      IReady                   => if_ready,                  -- [in  std_logic]
      OF_PipeRun               => of_PipeRun_Prefetch,       -- [in  std_logic]
      Jump                     => ex_jump,                   -- [in  boolean]
      WB_Dbg_exception         => WB_Dbg_exception,          -- [in  boolean]
      of_branch_with_delayslot => of_branch_with_delayslot,  -- [in  boolean]
      IB_Data                  => IB_Data,                   -- [in  DATA_TYPE]
      IB_Exception             => IB_Exception,              -- [in  std_logic]
      IF_Instr_Storage_Excep1  => IF_Instr_Storage_Excep1,   -- [in  std_logic]
      IF_Instr_TLB_Miss_Excep1 => IF_Instr_TLB_Miss_Excep1,  -- [in  std_logic]
      IF_Fetch_In_Progress     => if_fetch_in_progress,      -- [in  boolean]
      Valid_Fetch              => if_valid_fetch_s,          -- [out std_logic]
      OF_Valid                 => of_valid,                  -- [out boolean]
      Buffer_Full              => if_buffer_full,            -- [out boolean]
      OF_Instr                 => of_instr,                  -- [out DATA_TYPE]
      OF_PreDecode             => of_predecode, 
      OF_Instr_Exception       => of_instr_exception,        -- [out std_logic]
      OF_Instr_Storage_Excep   => of_Instr_Storage_Excep,    -- [out std_logic]
      OF_Instr_TLB_Miss_Excep  => of_Instr_TLB_Miss_Excep,   -- [out std_logic]
      IB_Buffer_En             => ib_buffer_en,              -- [out  slv_0to3]
      OF_Buffer_Sel            => of_buffer_sel              -- [out  slv_0to1]
      );
  --------------------------------------------------------------------------
  -- Decode Logic
  --------------------------------------------------------------------------

  --***************************************************************************
  --***************************************************************************
  --                   Instruction Fetch (IF) stage handling
  --***************************************************************************
  --***************************************************************************

  Using_ICache_Carry_Chain: if (C_USE_ICACHE) generate
  
    signal not_if_fetch_in_progress                 : std_logic;
    signal ib_ready_MMU_or_not_if_fetch_in_progress : std_logic;
    signal ib_addr_strobe_sel                       : std_logic;
    signal ib_addr_strobe_ii                        : std_logic;
  
  begin
    if_ready <= '1' when (ib_ready_MMU = '1') and if_valid else '0';

    ib_ready_MMU_carry_or : carry_or
      generic map (
        C_TARGET => C_TARGET)             -- [TARGET_FAMILY_TYPE]
      port map (
        Carry_IN  => IB_Ready,            -- [in  std_logic]
        A         => ib_excep_ready,      -- [in  std_logic]
        Carry_OUT => ib_ready_MMU);       -- [out std_logic]    
    
    -- Continue carry chain to generate ib_addr_strobe    
    -- ib_addr_strobe_i <= if_fetch_i and (Dbg_Stop_Instr_Fetch = '0') and
    --                     not (if_fetch_in_progress and (ib_Ready_MMU = '0'));
    not_if_fetch_in_progress <= '1' when not if_fetch_in_progress else '0';
    ib_addr_strobe_sel       <= '1' when if_fetch_i and (Dbg_Stop_Instr_Fetch = '0') else '0';
    
    ib_addr_strobe_i_carry_or : carry_or
      generic map (
        C_TARGET => C_TARGET)             -- [TARGET_FAMILY_TYPE]
      port map (
        Carry_IN  => ib_ready_MMU,                              -- [in  std_logic]
        A         => not_if_fetch_in_progress,                  -- [in  std_logic]
        Carry_OUT => ib_ready_MMU_or_not_if_fetch_in_progress); -- [out std_logic]    
        
    ib_addr_strobe_i_carry_and : carry_and
      generic map (
        C_TARGET => C_TARGET)             -- [TARGET_FAMILY_TYPE]
      port map (
        Carry_IN  => ib_ready_MMU_or_not_if_fetch_in_progress,  -- [in  std_logic]
        A         => ib_addr_strobe_sel,                        -- [in  std_logic]
        Carry_OUT => ib_addr_strobe_ii);                         -- [out std_logic]    
     
    ib_addr_strobe_i  <= ib_addr_strobe_ii = '1';
    
  end generate Using_ICache_Carry_Chain;

  No_ICache_Carry_Chain: if (not C_USE_ICACHE) generate
    if_ready <= '1' when (IB_Ready = '1' or ib_excep_ready = '1') and if_valid else '0';

    ib_Ready_MMU <= '1' when (IB_Ready = '1' or ib_excep_ready = '1') else '0';    
    
    ib_addr_strobe_i <= if_fetch_i and
                        not (if_fetch_in_progress and (ib_Ready_MMU = '0')) and
                        (Dbg_Stop_Instr_Fetch = '0');
  end generate No_ICache_Carry_Chain;

  ----------------------------------------
  -- IF_Fetch_In_Prog_PROCESS
  -- Need to know if a instruction fetch is progress
  ----------------------------------------
  IF_Fetch_In_Prog_PROCESS : process (Clk) is
  begin  -- process IB_Fetch_Bus_SM
    if Clk'event and Clk = '1' then  -- rising clock edge
      if reset_bool or (Dbg_Stop_Instr_Fetch = '1') then        
        if_fetch_in_progress <= false;
      elsif ib_addr_Strobe_i then
        -- Access starts (MMU look-up might delay bus access)
        if_fetch_in_progress <= true;
      elsif if_fetch_in_progress and (ib_Ready_MMU = '1') then
        if_fetch_in_progress <= false;
      end if;
    end if;
  end process IF_Fetch_In_Prog_PROCESS;

  if_fetch_i <= not reset_bool and (ex_return_to_VM = '0') and
                (not if_buffer_full or ex_jump) and (Dbg_Stop_Instr_Fetch = '0');
  ib_fetch_i <= '1' when if_fetch_i or if_fetch_in_progress else '0';
  IB_Fetch   <= ib_fetch_i;

  IB_Addr_Strobe   <= '1' when ib_addr_strobe_i else '0';

  ib_response_MMU <= IB_Addr_Strobe_MMU = '1'      or
                     IF_Instr_TLB_Miss_Excep = '1' or
                     IF_Instr_Storage_Excep  = '1';

  if_pc_write <= ib_response_MMU or ex_jump;

  -- Need to block increments of IB_PC while under debug stop and also delay it
  -- one clock cycle to allow the new_pc (which has been written to during the
  -- dbg stop by xmd) to be used as the first instruction fetch address after
  -- dbg has been released (step or continue)

  -- if_pc_incr  <= (not if_missed_fetch and
  --                   not (if_buffer_full and not if_addr_lookup_MMU)) and
  --                (Dbg_Stop_Instr_Fetch_delay = '0') and
  --                (not if_hold_incr_MMU);

  if_pc_incr1 <= '1' when not if_missed_fetch else '0';