decode_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

    EX_Data_Storage_Excep    : in  std_logic;  -- MMU Data storage exception
    EX_MMU_Stall             : in  boolean;    -- MMU stall of EX stage

    -- Result mux control signals
    EX_Sel_ALU          : out boolean;  -- EX mux select ALU
    EX_Sel_Shift        : out boolean;  -- EX mux select shift logic
    EX_Sel_FSL          : out boolean;  -- EX mux select fsl input
    MEM_Sel_Barrel      : out boolean;  -- MEM mux select barrel shifter
    MEM_Sel_Div         : out boolean;  -- MEM mux select div unit
    MEM_Sel_MSR         : out boolean;  -- MEM mux select EX MSR
    MEM_Sel_EX_Res      : out boolean;  -- MEM mux select EX result
    MEM_Sel_MEM_Res     : out boolean;  -- MEM mux select result from MEM stage
    WB_Sel_SPR_ESR      : out boolean;  -- WB mux select SPR exception status register
    WB_Sel_SPR_EAR      : out boolean;  -- WB mux select SPR exception address register
    WB_Sel_SPR_EDR      : out boolean;  -- WB mux select SPR exception data register
    WB_Sel_SPR_FSR      : out boolean;  -- WB mux select SPR FPU status register
    WB_Sel_SPR_PVR      : out boolean;  -- WB mux select SPR processor version register
    WB_Sel_SPR_BTR      : out boolean;  -- WB mux select SPR Branch Target register
    WB_Sel_DataBus_Read_Data : out boolean;  -- WB mux select DB_Read_Data
    WB_Sel_MEM_Res      : out boolean;  -- WB mux select result from MEM stage
    WB_Sel_MUL_Res      : out boolean;  -- WB mux select result from Multiplier
    WB_Sel_FPU_Res      : out boolean;  -- WB mux select result from FPU
    WB_Exception_Taken  : out boolean;  -- Take exception (WB stage)

    -- Select which PVR to read
    MEM_PVR_Select  : out std_logic_vector(0 to 3);  -- Select which PVR to read
    MEM_Sel_SPR_PVR : out boolean;                   -- Select SPR processor version register

    -- Zero detect signals
    EX_Op1_CMP_Equal    : out boolean;   -- Test for equality
    EX_Op1_CMP_Equal_n  : out boolean;   -- Test for inequality
    EX_Op1_Zero         : in  boolean;   -- Is Ra zero?
    EX_Op1_Neg          : in  boolean;   -- Is Ra negative?

    -- PC module signals
    OF_PC : out DATA_TYPE;               -- OF stage program counter

    -- Cache signals
    WB_Write_ICache   : out boolean;     -- WIC instruction write to icache
    WB_Write_DCache   : out boolean;     -- WDC instruction write to dcache
    ICache_Idle       : in  boolean;     -- Icache idle so WIC can proceed
    DCache_Idle       : in  boolean;     -- Dcache idle so WDC can proceed
    ICACHE_Valid_Req  : in  boolean;     -- Valid request from icache
    IF_Valid_Req_Prev : out std_logic;   -- Previous valid icache request followed by a jump

    -- Debug signals
    EX_Dbg_PC_Hit        : in  boolean;  -- True for a valid PC breakpoint
    Dbg_State            : in  boolean;  -- MicroBlaze is in Debug state
    Dbg_freeze           : in  boolean;  -- MicroBlaze is in Debug state
    Dbg_Stop_Instr_Fetch : in  std_logic;  -- Debug stop instruction fetch (set on WB_Halted)
    Dbg_Want_To_Break_FSL: in  std_logic;  -- Debug needs to break a blocked FSL instruction
    FSL_Will_Dbg_Break   : out std_logic; -- Blocked FSL instruction will be breaked by dbg
    EX_Exception_Taken   : out boolean;  -- Exception/Debug/Interrupt taken
    WB_PC                : out DATA_TYPE;  -- PC in WB stage
    WB_Halted            : out boolean;  -- Debug condition has reached WB and MicroBlaze is halted
    WB_GPR_Wr_Dbg        : out boolean;  -- Write to debug data_rd_reg when in debug state
    OF_Valid_Instr       : out boolean;  -- Valid instruction is OF stage
    WB_DelaySlot_Instr   : out boolean;  -- Delay slot instruction in WB stage
    WB_Read_Imm_Reg      : out boolean;  -- Instruction that uses Imm in WB stage
    WB_Read_Imm_Reg_1    : out boolean;  -- Previous instruction in WB stage used Imm
    WB_PC_Valid          : out std_logic;  -- PC in WB stage is valid

    -- Exception signals
    EX_PC                    : out DATA_TYPE;  -- Program counter (instruction address) in execute stage
    EX_Addr_Low_Bits         : in  std_logic_vector(0 to 1);
    EX_Instruction_Exception : out boolean;
    EX_Load_BTR              : out boolean;
    MEM_Sel_SPR_BTR          : out  boolean;  -- Select SPR Branch Target Register
    MEM_Sel_SPR_ESR          : out  boolean;  -- Select SPR exception status register
    MEM_Sel_SPR_EAR          : out  boolean;  -- Select SPR exception address register
    MEM_Sel_SPR_EDR          : out  boolean;  -- Select SPR exception data register
    WB_Clr_ESR               : out boolean;
    WB_Load_EAR              : out boolean;
    WB_Load_EDR              : out boolean;
    WB_Load_ESR              : out boolean;
    WB_Exception_Kind        : out EXCEPTION_KIND_TYPE;
    WB_SW_Instr              : out std_logic;
    WB_Word_Access           : out std_logic;
    WB_New_ESR_ESS_Rx        : out GPR_ADDR_TYPE;

    -- FSL signals
    FSL_Get                  : out std_logic;  -- A FSL get instruction
    FSL_Get_Test             : out std_logic;  -- This is a test instruction.
    FSL_Get_Inhibit          : out std_logic;  -- FSL Get must not execute (exceptions, ....)
    FSL_Get_Control          : out std_logic;  -- The get control bit from the FSL instruction
    FSL_Get_Blocking         : out std_logic;  -- The FSL get instruction is blocking
    FSL_Get_Break            : out std_logic;  -- The FSL is breaked
    FSL_Get_Succesful        : in  std_logic;  -- The FSL get was succesful
    FSL_Put                  : out std_logic;  -- A FSL put instruction
    FSL_Put_Test             : out std_logic;  -- This is a test instruction.
    FSL_Put_Inhibit          : out std_logic;  -- FSL Put must not execute (exceptions, ....)
    FSL_Put_Control          : out std_logic;  -- The put control bit from the FSL instruction
    FSL_Put_Blocking         : out std_logic;  -- The FSL get instruction is blocking
    FSL_Put_Break            : out std_logic;  -- The FSL is breaked
    FSL_Put_Succesful        : in  std_logic;  -- The FSL put was succesful
    FSL_Stall                : in  std_logic;  -- A blocking FSL instruction is
    EX_FSL_Control_Error     : in  std_logic;  -- A FSL Get control bit mismatch has occured

    -- Trace signals
    Trace_WB_Valid_Instr : out std_logic;   -- Valid instruction in WB stage
    Trace_WB_Instr       : out DATA_TYPE;   -- Instr in WB stage
    Trace_WB_Jump_Taken  : out std_logic    -- Jump taken in EX stage  but that
                                            -- instruction is now in WB stage
    );
end entity Decode_gti;

--------------------------------------------------------------------------
-- Architecture section
--------------------------------------------------------------------------

architecture IMP of Decode_gti is

  -----------------------------------------------------------------------------
  -- Constant declarations
  -----------------------------------------------------------------------------
  constant C_IEXT_BUS_EXCEPTION : boolean := C_IOPB_BUS_EXCEPTION or
                                             C_IPLB_BUS_EXCEPTION;

  constant FSL_EXCEPTION_ON     : boolean := ( C_FSL_LINKS > 0 ) and ( C_FSL_EXCEPTION ) and ( C_USE_EXTENDED_FSL_INSTR /= 0 );
  
  constant C_EXCEPTIONS_EXCEPT_INTERRUPT :
    boolean := C_UNALIGNED_EXCEPTIONS or C_ILL_OPCODE_EXCEPTION or
               C_IOPB_BUS_EXCEPTION   or C_DOPB_BUS_EXCEPTION   or
               C_IPLB_BUS_EXCEPTION   or C_DPLB_BUS_EXCEPTION   or
               C_DIV_ZERO_EXCEPTION   or C_FPU_EXCEPTION        or
               FSL_EXCEPTION_ON       or C_USE_MMU > C_MMU_NONE;

  constant C_USE_ICACHE_WR : boolean := C_ALLOW_ICACHE_WR and C_USE_ICACHE;
  constant C_USE_DCACHE_WR : boolean := C_ALLOW_DCACHE_WR and C_USE_DCACHE;

  -----------------------------------------------------------------------------
  -- Component declarations
  -----------------------------------------------------------------------------

  component PC_Module_gti is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE
      -- pragma xilinx_rtl_off
;
      C_U_SET  : string
      -- pragma xilinx_rtl_on
      );
    port (
      Clk   : in std_logic;
      Reset : in std_logic;

      IF_Valid_Fetch : in boolean;
      OF_PipeRun     : in boolean;
      EX_PipeRun        : in  boolean;
      MEM_PipeRun       : in  boolean;

      IF_PC_Incr : in boolean;

      EX_Jump       : in boolean;
      EX_ALU_Result : in DATA_TYPE;

      IF_PC_Write   : in  boolean;
      IB_Buffer_En  : in  slv_0to3;
      OF_Buffer_Sel : in  slv_0to1;

      OF_PC   : out DATA_TYPE;
      EX_PC   : out DATA_TYPE;
      WB_PC   : out DATA_TYPE;
      IB_Addr : out DATA_TYPE
      );
  end component PC_Module_gti;

  component PreFetch_Buffer_gti is
    generic (
      C_IEXT_BUS_EXCEPTION : boolean;
      C_USE_MMU            : integer);
    port (
      Clk                      : in  std_logic;
      Reset                    : in  boolean;
      IReady                   : in  std_logic;
      OF_PipeRun               : in  std_logic;
      Jump                     : in  boolean;
      WB_Dbg_exception         : in  boolean;
      IB_Data                  : in  DATA_TYPE;
      IB_Exception             : in  std_logic;
      IF_Instr_Storage_Excep1  : in  std_logic;
      IF_Instr_TLB_Miss_Excep1 : in  std_logic;
      IF_Fetch_In_Progress     : in  boolean;
      of_branch_with_delayslot : in  boolean;
      Valid_Fetch              : out std_logic;
      OF_Valid                 : out boolean;
      Buffer_Full              : out boolean;
      OF_Instr                 : out DATA_TYPE;
      OF_PreDecode             : out std_logic_vector(0 to 10);
      OF_Instr_Exception       : out std_logic;
      OF_Instr_Storage_Excep   : out std_logic;
      OF_Instr_TLB_Miss_Excep  : out std_logic;
      IB_Buffer_En             : out slv_0to3;
      OF_Buffer_Sel            : out slv_0to1
      );
  end component PreFetch_Buffer_gti;

  component Jump_Logic is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE);
    port (
      Clk   : in std_logic;
      Reset : in std_logic;

      OF_PipeRun : in boolean;
      EX_PipeRun : in boolean;

      OF_Valid : in boolean;
      OF_instr : in DATA_TYPE;

      EX_which_branch                 : in std_logic_vector(BXX_POS_TYPE);
      EX_Opcode                       : in OPCODE_TYPE;
      EX_Missed_Fetch_on_Branch_Ended : in boolean;
      EX_Branch_With_Delayslot        : in boolean;
      EX_Take_Intr_or_Exc             : in boolean;
      EX_Valid                        : in boolean;
      EX_Exception                    : in boolean;
      EX_Op1_Neg                      : in boolean;
      EX_Op1_Zero                     : in boolean;
      IF_Addr_Lookup_MMU              : in boolean;

      EX_Op1_CMP_Equal   : out boolean;
      EX_Op1_CMP_Equal_n : out boolean;

      EX_Jump_Stall : out boolean;
      EX_Jump       : out boolean);
  end component Jump_Logic;

  component carry_and is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE);
    port (
      Carry_IN  : in  std_logic;
      A         : in  std_logic;
      Carry_OUT : out std_logic);
  end component carry_and;

  component carry_or is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE);
    port (
      Carry_IN  : in  std_logic;
      A         : in  std_logic;
      Carry_OUT : out std_logic);
  end component carry_or;
  
  -----------------------------------------------------------------------------
  -- Internal signal declarations
  -----------------------------------------------------------------------------

  -----------------------------------------------------------------------------
  -- Global signals
  -----------------------------------------------------------------------------
  signal reset_bool : boolean;
  signal flush_pipe : boolean;

  -----------------------------------------------------------------------------
  -- Signals for IF stage
  -----------------------------------------------------------------------------

  signal if_ready             : std_logic;
  signal ib_Ready_MMU         : std_logic;

  signal ib_buffer_en         : slv_0to3;
  signal ib_addr_strobe_i     : rboolean;
  signal ib_fetch_i           : std_logic;
  signal if_fetch_in_progress : boolean;
  signal if_fetch_i           : boolean;
  signal if_pc_incr           : boolean;
  signal if_pc_incr1          : std_logic;
  signal if_pc_incr2          : std_logic;
  signal if_pc_incr3          : std_logic;
  signal if_pc_incr4          : std_logic;
  signal if_pc_incr_carry1    : std_logic;
  signal if_pc_incr_carry2    : std_logic;
  signal if_pc_incr_carry3    : std_logic;
  signal ib_response_MMU      : boolean;
  signal if_pc_write          : boolean;
  signal if_buffer_full       : boolean;
  signal if_valid_fetch_i     : boolean;
  signal if_valid_fetch_s     : std_logic;

  signal if_missed_fetch                : boolean;
  signal if_missed_fetch_already_tested : boolean;
  signal if_valid                       : boolean;

  signal if_jump_nodelay_rst  : boolean;

  signal dbg_Stop_Instr_Fetch_delay : std_logic;