decode_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: decode_gti.vhd,v 1.8 2007/12/17 16:39:59 stefana Exp $
-------------------------------------------------------------------------------
-- decode_gti.vhd - Entity and architecture
--
--  **************************************************************************
--  **  Copyright(C) 2001-2005 by Xilinx, Inc. All rights reserved.          **
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--  **  function and run at speed according to the datasheet                 **
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--  **  obligation on the part of Xilinx to provide support.                 **
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--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
--  **                                                                       **
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--  **  to confirm the problem in the Netlist version of the core.           **
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--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        decode_gti.vhd
-- Version:         v2.00a
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              decode_gti.vhd
--                        -- PC Module
--                        -- Prefetch Buffer
--
-------------------------------------------------------------------------------
-- Author:          goran
--
-- History:
--   goran  2005-03-22    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY_>I_<#|FUNC>" , "ENTITY>_I#" 
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                                -- instruction fetch
--    OF                                -- operand fetch
--    EX                                -- execute
--    MEM                               -- memory
--    WB                                -- write back
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types and ISA constants
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity Decode_gti is
  generic (
    C_TARGET               : TARGET_FAMILY_TYPE; -- Device family
    -- pragma xilinx_rtl_off
    C_U_SET                : string := "decode"; -- Name of unit
    -- pragma xilinx_rtl_on
    C_PVR                  : integer;   -- Which PVR mode None=0, Basic=1, Full=2
    C_DEBUG_ENABLED        : boolean;   -- Enable debug
    C_USE_ICACHE           : boolean;   -- Enable instruction cache
    C_ALLOW_ICACHE_WR      : boolean;   -- Allow instruction cache write with WIC
    C_USE_DCACHE           : boolean;   -- Enable data cache
    C_ALLOW_DCACHE_WR      : boolean;   -- Allow Data cache write with WDC
    C_USE_BARREL           : boolean;   -- Use barrel shifter
    C_USE_MSR_INSTR        : boolean;   -- Enable msrxxx instructions
    C_USE_DIV              : boolean;   -- Enable divider
    C_USE_FPU              : integer;   -- Enable FPU
    C_USE_MMU              : integer;   -- Enable MMU
    C_MMU_TLB_READ         : boolean;   -- Use MMU TLB read
    C_FSL_LINKS            : integer;   -- Number of FSL links
    C_USE_EXTENDED_FSL_INSTR  : integer := 0; -- If the new FSL instructions should be used
    C_UNALIGNED_EXCEPTIONS : boolean;   -- Enable unaligned exceptions
    C_ILL_OPCODE_EXCEPTION : boolean;   -- Enable illegal opcode exception
    C_DETECT_OPCODE_0x0    : boolean;   -- Make opcode 0x0000_0000 illegal
    C_IOPB_BUS_EXCEPTION   : boolean;   -- Enable instruction OPB bus exception
    C_DOPB_BUS_EXCEPTION   : boolean;   -- Enable data OPB bus exception
    C_IPLB_BUS_EXCEPTION   : boolean;   -- Enable instruction PLB bus exception
    C_DPLB_BUS_EXCEPTION   : boolean;   -- Enable data PLB bus exception
    C_DIV_ZERO_EXCEPTION   : boolean;   -- Enable divide by zero exception
    C_FPU_EXCEPTION        : boolean;   -- Enable floating point exception
    C_FSL_EXCEPTION        : boolean;   -- Enable FSL control mismatch exception
    C_USE_MUL_INSTR        : boolean;   -- Enable mul instruction
    C_USE_MUL64            : boolean;   -- Enable 64-bit multiplication
    C_USE_PCMP_INSTR       : boolean  --;         -- Enable pattern compare instructions
    );
  port (
    Clk   : in std_logic;                -- Clock
    Reset : in std_logic;                -- internal reset

    -- External break inputs
    Ext_BRK    : in std_logic;
    Ext_NM_BRK : in std_logic;

    -- Interrupt
    Internal_interrupt    : in  boolean;  -- Interrupt signal converted (External interrupt converted)
    Dbg_Disable_Interrupt : in  boolean;  -- Debug logic control register interrupts disabled
    WB_Interrupt_Taken    : out std_logic;  -- WB is taking an interrupt

    -- Instruction bus control
    IB_Addr            : out DATA_TYPE;  -- Instruction bus address
    IB_Fetch           : out std_logic;  -- Instruction bus fetch
    IB_Addr_Strobe     : out std_logic;  -- Instruction bus address strobe
    IB_Ready           : in  std_logic;  -- Instruction bus ready
    IB_Data            : in  DATA_TYPE;  -- Instruction bus data
    IB_Exception       : in  std_logic;  -- Instruction bus exception
    IB_Addr_Strobe_MMU : in  std_logic;  -- Instruction bus address strobe
    IB_VMode           : out std_logic;  -- Instruction bus virtual mode
    IB_UMode           : out std_logic;  -- Instruction bus user mode

    --  Data bus control
    EX_DataBus_Addr     : out DATA_TYPE;  -- Address for data bus
    EX_DataBus_Access   : out std_logic;  -- Data bus access
    EX_DataBus_Read     : out std_logic;  -- Data bus read
    EX_DataBus_Write    : out std_logic;  -- Data bus write
    EX_DataBus_Addr_MMU : in  DATA_TYPE;  -- Physical Address for data bus
    MEM_DataBus_Addr    : out DATA_TYPE;  -- Address for data bus
    MEM_DataBus_Access  : out std_logic;  -- Data bus access
    MEM_DataBus_Read    : out std_logic;  -- Data bus read
    MEM_DataBus_Write   : out std_logic;  -- Data bus write

    MEM_DataBus_Ready       : in  std_logic;  -- Data bus ready
    MEM_DataBus_Exception   : in  std_logic;  -- Data bus exception

    WB_Byte_Access    : out boolean;  -- Read on data bus is 8-bits
    WB_Doublet_Access : out boolean;  -- Read on data bus is 16-bits
    WB_Quadlet_Access : out boolean;  -- Read on data bus is 32-bits
    EX_Byte_Access    : out boolean;  -- Data bus 8-bit write
    EX_Doublet_Access : out boolean;  -- Data bus 16-bit write

    -- Pipeline control
    OF_PipeRun  : out boolean;           -- Move the operand fetch stage
    EX_PipeRun  : out boolean;           -- Move the execute stage
    MEM_PipeRun : out boolean;           -- Move the memory stage
    WB_PipeRun  : out boolean;           -- Move the write back stage

    -- Register File signals
    WB_GPR_Wr_Addr     : out GPR_ADDR_TYPE; -- General Purpose Register write address
    WB_GPR_Wr          : out boolean;       -- General Purpose Register write strobe

    OF_GPR_Op1_Rd_Addr : out GPR_ADDR_TYPE; -- General Purpose Register read address for Op1
    OF_GPR_Op2_Rd_Addr : out GPR_ADDR_TYPE; -- General Purpose Register read address for Op2
    OF_GPR_Op3_Rd_Addr : out GPR_ADDR_TYPE; -- General Purpose Register read address for Op3

    -- Operand select control signals
    OF_Op1_Sel_SPR_PC  : out boolean;  -- Op1 select SPR program counter
    OF_Op1_Sel_SPR_MSR : out boolean;  -- Op1 select SPR machine status register
    OF_Op1_Sel_SPR     : out boolean;  -- Op1 select SPR
    OF_Op2_Sel_Imm     : out boolean;

    OF_Op1_Sel         : out std_logic_vector(0 to 1);  -- Op1 select 
    OF_Op2_Sel         : out std_logic_vector(0 to 1);  -- Op2 select 
    OF_Op3_Sel         : out std_logic_vector(0 to 1);  -- Op3 select 

    OF_Write_Imm_Reg  : out boolean;  -- Immediate register write strobe (Imm_Instr)
    OF_Read_Imm_Reg   : out boolean;  -- Immediate register read strobe (Use_Imm_Reg)
    OF_Imm_Data       : out IMM16_TYPE;  -- Opcode immediate data (Imm_Value)
    OF_Take_Interrupt : out boolean;
    OF_Take_Ext_BRK   : out boolean;
    OF_Take_Exception : out boolean;

    -- Arith control signals
    EX_CMP_Op       : out boolean;       -- CMP operation
    EX_Unsigned_Op  : out boolean;       -- Unsigned arithmetic operation (CMPU and IDIVU)
    EX_Use_Carry    : out boolean;       -- Arithemic operation with carry
    EX_ALU_Op       : out ALU_OP_TYPE;   -- Which ALU operation to perform
    EX_ALU_Result   : in  DATA_TYPE;     -- Result from ALU

    -- Logic Shift control signals
    EX_Sext_Op              : out  SEXT_OP_TYPE;  -- Sign extension operation (Op1, 8, 16)
    EX_Shift_Op             : out  SHIFT_OP_TYPE; -- Shift operation (SRA, SRC, SRL, SEXT)
    EX_Logic_Op             : out  LOGIC_OP_TYPE; -- Logic operation (or, and, xor, andn)
    EX_Sign_Extend_Sel      : out  boolean;       -- Shift Logic Mux, select Sign Extension
    EX_Pattern_Cmp_Sel      : out  boolean;       -- Shift Logic Mux, select PCMP Result
    EX_Logic_Sel            : out  boolean;       -- Shift Logic Mux, select Logic Result 

    -- SPR control
    EX_MSR_Load_ALU_C   : out std_logic;  -- Arithemetic operation update carry
    EX_MSR_Load_Shift_C : out std_logic;  -- Shift operation update carry
    EX_MSR_Load_FSL_C   : out std_logic;  -- FSL operation update carry
    EX_MSR_Set_IE       : out std_logic;  -- Set interrupt enable on rti
    EX_MSR_Set_EE       : out std_logic;  -- Set exception enable on rted
    EX_MSR_Clear_EIP    : out std_logic;  -- Clear exception in progress on rted
    EX_MSR_Set_SW_BIP   : out std_logic;  -- Set BIP on taking BRK, BRKI
    EX_MSR_Clear_BIP    : out std_logic;  -- Clear break in progress on rtbd
    EX_MSR_Clear_VM_UM  : out std_logic;  -- Clear VM and UM bits
    EX_MTS_MSR          : out std_logic;  -- MTS instruction accessing MSR
    EX_MTS_FSR          : out std_logic;  -- MTS instruction accessing FSR
    EX_Restore_WB_MSR   : out std_logic;  -- Restore WB MSR to EX stage (exceptions)
    EX_MSRCLR           : out std_logic;  -- MSRCLR instruction
    EX_MSRSET           : out std_logic;  -- MSRSET instruction
    MEM_MSR_Load_DZ     : out std_logic;  -- IDIV load divide by zero, not used
    WB_MSR_Clear_IE     : out std_logic;  -- Clear IE on taking interrupt
    WB_MSR_Clear_EE     : out std_logic;  -- Clear EE on taking exception
    WB_MSR_Set_EIP      : out std_logic;  -- Set EIP on taking exception
    WB_MSR_Set_HW_BIP   : out std_logic;  -- Set BIP on ext_brk, ext_nm_brk

    -- MSR register values
    OF_MSR              : in  DATA_TYPE; -- EX stage MSR value
    EX_MSR              : in  DATA_TYPE; -- EX stage MSR value
    MEM_MSR             : in  DATA_TYPE; -- MEM stage MSR value
    WB_MSR              : in  DATA_TYPE; -- WB stage MSR value

    -- Multiplier
    EX_Not_Mul_Op   : out boolean;      -- EX stage instruction not a multiply
    EX_Mulh_Instr   : out boolean;      -- Multiply high instruction
    EX_Mulhu_Instr  : out boolean;      -- Unsigned multiply high instruction
    EX_Mulhsu_Instr : out boolean;      -- Signed * Unsigned multiply high instruction

    -- Barrel Shifter
    -- EX_Not_Barrel_Op    : out boolean;    -- Disable barrel shifter
    EX_Is_BS_Instr      : out boolean;
    EX_Left_Shift       : out boolean;    -- Select left/right shift (side)
    EX_Arith_Shift      : out boolean;    -- Arithmetic/logical shift (type)

    -- Div Unit
    EX_Is_Div_Instr : out boolean;
    EX_Start_Div    : out boolean;
    EX_Div_Unsigned : out boolean;
    MEM_Is_Div_Instr: out boolean;
    MEM_Div_By_Zero : in  boolean;
    MEM_Div_Stall   : in  boolean;

    -- FPU
    EX_FPU_Op         : out FPU_OP_TYPE;
    EX_FPU_Cond       : out FPU_COND_TYPE;
    EX_Start_FPU      : out boolean;
    EX_Not_FPU_Instr  : out boolean;
    MEM_Sel_SPR_FSR   : out boolean;         -- Select SPR floating point status register
    MEM_FPU_Stall     : in  boolean;
    MEM_FPU_Excep     : in  boolean;

    -- MMU
    EX_MTS_PID               : out std_logic;  -- MTS instruction accessing PID
    EX_MTS_ZPR               : out std_logic;  -- MTS instruction accessing ZPR
    EX_MTS_TLBX              : out std_logic;  -- MTS instruction accessing TLBX
    EX_MTS_TLBLO             : out std_logic;  -- MTS instruction accessing TLBLO
    EX_MTS_TLBHI             : out std_logic;  -- MTS instruction accessing TLBHI
    EX_MTS_TLBSX             : out std_logic;  -- MTS instruction accessing TLBSX
    EX_Sel_SPR_TLBLO         : out boolean;    -- MFS instruction accessing TLBLO
    EX_Sel_SPR_TLBHI         : out boolean;    -- MFS instruction accessing TLBHI
    MEM_Sel_SPR_PID          : out boolean;    -- MFS instruction accessing PID
    MEM_Sel_SPR_ZPR          : out boolean;    -- MFS instruction accessing ZPR
    MEM_Sel_SPR_TLBX         : out boolean;    -- MFS instruction accessing TLBX
    MEM_Sel_SPR_TLBLO        : out boolean;    -- MFS instruction accessing TLBLO
    MEM_Sel_SPR_TLBHI        : out boolean;    -- MFS instruction accessing TLBHI
    IF_Instr_TLB_Miss_Excep  : in  std_logic;  -- MMU Instruction TLB miss exception
    IF_Instr_Storage_Excep   : in  std_logic;  -- MMU Instruction storage exception
    EX_Data_TLB_Miss_Excep   : in  std_logic;  -- MMU Data TLB miss exception