register_file_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: register_file_gti.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- register_file.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2001-2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc. 
-- **
-- ** Unmodified source code is guaranteed to place and route, 
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: register_file.vhd
-- Version: v2.00a
-- Description: Implements the 32x32 Register File
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              register_file.vhd
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--   BJS    2005-03-28
-- ^^^^^^
--                        Updated for new pipeline
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY_>I_<#|FUNC>" , "ENTITY>_I#" 
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                      -- instruction fetch
--    OF                      -- operand fetch
--    EX                      -- execute
--    MEM                     -- memory
--    WB                      -- write back
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types and ISA constants
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
--
--    C_TARGET                -- Device family
--    C_U_SET                 -- Name of unit
--
-- Definition of Ports:
--
--    Clk                     -- Clock
--
--    OF_GPR_Op1_Rd_Addr      -- General Purpose Register read address for Op1
--    GPR_Op1                 -- General Purpose Register operand 1
--
--    OF_GPR_Op2_Rd_Addr      -- General Purpose Register read address for Op2
--    GPR_Op2                 -- General Purpose Register operand 2
--
--    WB_GPR_Wr_Addr          -- General Purpose Register write address
--    WB_GPR_Wr               -- General Purpose Register write strobe
--    WB_Fwd                  -- Write back stage forwarding
--    GPR_Read_For_Stores     -- Read port for non-imm store instructions
--
-------------------------------------------------------------------------------
entity Register_File_gti is
  generic (
    C_TARGET : TARGET_FAMILY_TYPE
    -- pragma xilinx_rtl_off
;
    C_U_SET  : string
   -- pragma xilinx_rtl_on
    );
  port (
    Clk : in std_logic;

    OF_GPR_Op1_Rd_Addr : in  GPR_ADDR_TYPE;
    GPR_Op1            : out DATA_TYPE;

    OF_GPR_Op2_Rd_Addr : in  GPR_ADDR_TYPE;
    GPR_Op2            : out DATA_TYPE;

    OF_GPR_Op3_Rd_Addr : in  GPR_ADDR_TYPE;
    GPR_Op3            : out DATA_TYPE;

    WB_GPR_Wr_Addr : in GPR_ADDR_TYPE;
    WB_GPR_Wr      : in boolean;
    WB_Fwd         : in DATA_TYPE
   -- GPR_Read_For_Stores : out DATA_TYPE
    );
end entity Register_File_gti;

--------------------------------------------------------------------------
-- Architecture section
--------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;

architecture IMP of Register_File_gti is
  -- Inferred register file
  type REG_FILE_TYPE is array(0 to 31) of DATA_TYPE;
  signal Reg_File : REG_FILE_TYPE := (others => (others => '0'));
  signal WB_GPR_Wr_std : std_logic;
  
begin

  WB_GPR_Wr_std <= '1' when WB_GPR_Wr else '0';
  
  Using_Virtex5 : if (C_TARGET = VIRTEX5) generate
    ---------------------------------------------------------------------------
    -- Instantiating the RAM32M primitives
    ---------------------------------------------------------------------------
    All_RAM32M : for I in 0 to 15 generate
      ram32m_i : RAM32M
        port map (
          WCLK  => Clk,
          WE    => WB_GPR_Wr_std,
          ADDRD => WB_GPR_Wr_Addr,
          ADDRA => OF_GPR_Op1_Rd_Addr,
          ADDRB => OF_GPR_Op2_Rd_Addr,
          ADDRC => OF_GPR_Op3_Rd_Addr,

          DIA => WB_Fwd(I*2 to I*2+1),
          DIB => WB_Fwd(I*2 to I*2+1),
          DIC => WB_Fwd(I*2 to I*2+1),
          DID => WB_Fwd(I*2 to I*2+1),

          DOA => GPR_Op1(I*2 to I*2+1),
          DOB => GPR_Op2(I*2 to I*2+1),
          DOC => GPR_Op3(I*2 to I*2+1),
          DOD => open
          );
    end generate All_RAM32M;

  end generate Using_Virtex5;

  Not_Using_Virtex5 : if (C_TARGET /= VIRTEX5) generate
    ----------------------------------------
    -- Reg_File_Infer
    -- Register file
    -- xst should infer a multi-port distributed RAM
    ----------------------------------------
    Reg_File_Infer : process (Clk) is
    begin  -- process Reg_File_Handle
      if Clk'event and Clk = '1' then   -- rising clock edge
        if WB_GPR_WR then               -- write enable
          Reg_File(to_integer(unsigned(WB_GPR_Wr_Addr))) <= WB_Fwd;
        end if;
      end if;
    end process Reg_File_Infer;

    GPR_Op1 <= Reg_File(to_integer(unsigned(OF_GPR_Op1_Rd_Addr)));
    GPR_Op2 <= Reg_File(to_integer(unsigned(OF_GPR_Op2_Rd_Addr)));
    GPR_Op3 <= Reg_File(to_integer(unsigned(OF_GPR_Op3_Rd_Addr)));
  end generate Not_Using_Virtex5;

end architecture IMP;