byte_doublet_handle_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: byte_doublet_handle_gti.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- byte_doublet_handle.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2001-2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc. 
-- **
-- ** Unmodified source code is guaranteed to place and route, 
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: byte_doublet_handle.vhd
-- Version: v2.00a
-- Description: Handles write data mirroring and read data steering
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              byte_doublet_handle.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--   BLT    2001-04-16
-- ^^^^^^
--                        Modified M_DBus FF's to be synch reset
-- ~~~~~~
--   BLT    2001-04-23
-- ^^^^^^
--                        Forced Read_LSB mux to use F5MUX
-- ~~~~~~
--   goran  2002-05-10
-- ^^^^^^
--                        Remove all ISA usage and mux_encode_sel
--      1. Modified sel_LSB_1 in Extend_Data_Read_Sel_LSB_1 to use
--         Low_Addr'left instead of Low_Addr'right
--      2. Modified sel_LSB in Extend_Data_Read_Sel_LSB to use
--         Low_Addr(Low_Addr'left) instead of Low_Addr(1)
--      3. Use mux_encode_sel for Extend_Data_Read_Mux_LSB
--      4. Remove all usage of mux_encode_sel and added fixed size muxes
--         Needed to pass XST
-- ~~~~~~
--   BJS    2005-03-28
-- ^^^^^^
--                        Updated for new pipeline
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY_>I_<#|FUNC>" , "ENTITY>_I#" 
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                      -- instruction fetch
--    OF                      -- operand fetch
--    EX                      -- execute
--    MEM                     -- memory
--    WB                      -- write back
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
--
--    C_TARGET                -- Device family
--    C_U_SET                 -- Name of unit
--
-- Definition of Ports:
--
--    EX_Byte_Access          -- Data bus 8-bit write
--    EX_Doublet_Access       -- Data bus 16-bit write
--
--    EX_Op1_2LSb             -- 2 least significants bits of EX stage operand 1
--    EX_Op2_2LSb             -- 2 least significants bits of EX stage operand 2
--
--    EX_Op3                  -- Data to be written that needs to be mirrored
--    DB_Write_Data           -- Data to be written after mirroring
--    DB_Byte_Enable          -- Data bus byte enables
--    DB_Aligned_Addr_2LSb    -- 2 LSb of data bus address aligned for current access
--
--    EX_UnAlign_2LSb         -- EX stage unaligned bytes and doublets
--    WB_UnAlign_2LSb         -- WB stage unaligned bytes and doublets
--
--    WB_Byte_Access          -- Data bus 8-bit read
--    WB_Doublet_Access       -- Data bus 16-bit read
--
--    DB_Read_Data            -- Data read from bus
--    Steered_Read_Data       -- Data read after read steering
--
-------------------------------------------------------------------------------
entity Byte_Doublet_Handle_gti is
  generic (
    C_TARGET : TARGET_FAMILY_TYPE
    -- pragma xilinx_rtl_off
;
    C_U_SET  : string
    -- pragma xilinx_rtl_on
    );
  port (
    Clk        : in std_logic;
    Reset      : in std_logic;
    EX_PipeRun : in boolean;

    EX_Op1_2LSb : in slv_0to1;
    EX_Op2_2LSb : in slv_0to1;

    EX_Byte_Access    : in boolean;
    EX_Doublet_Access : in boolean;

    EX_Op3                       : in  DATA_TYPE;
    EX_DataBus_Write_Data        : out DATA_TYPE;
    EX_DataBus_Byte_Enable       : out DATA_BE_TYPE;
    MEM_DataBus_Write_Data       : out DATA_TYPE;
    MEM_DataBus_Byte_Enable      : out DATA_BE_TYPE;

    EX_Addr_Low_Bits : out slv_0to1;
    EX_UnAlign_2LSb : out slv_0to1;
    WB_UnAlign_2LSb : in  slv_0to1;

    WB_Byte_Access    : in boolean;
    WB_Doublet_Access : in boolean;

    WB_DataBus_Read_Data : in  DATA_TYPE;
    WB_Steered_Read_Data : out DATA_TYPE
    );
end entity Byte_Doublet_Handle_gti;

--------------------------------------------------------------------------
-- Architecture section
--------------------------------------------------------------------------

architecture IMP of Byte_Doublet_Handle_gti is
  -- Are the LSb unaligned?
  signal ex_unaligned_Addr_2LSb   : slv_0to1;
  signal ex_DataBus_Write_Data_i  : DATA_TYPE;
  signal ex_DataBus_Byte_Enable_i : DATA_BE_TYPE;
  signal ex_word_access : boolean;
  signal wb_word_access : boolean;
begin

  -- early result from the address+offset ALU calculation
  -- ex_unaligned_Addr_2LSb <= EX_Op1_2LSb + EX_Op2_2LSb;
  ex_unaligned_Addr_2LSb(0) <= EX_Op1_2LSb(0) xor EX_Op2_2LSb(0) xor
                               (EX_Op1_2LSb(1) and EX_Op2_2LSb(1));
  ex_unaligned_Addr_2LSb(1) <= EX_Op1_2LSb(1) xor EX_Op2_2LSb(1);

  EX_Addr_Low_Bits <= ex_unaligned_Addr_2LSb;
  
  ----------------------------------------
  -- Write_Data_Mirror_PROCESS
  -- Mirrored data
  ----------------------------------------
  Write_Data_Mirror_PROCESS : process (EX_Byte_Access, EX_Doublet_Access, EX_Op3) is
  begin  -- process Write_Data_Mirror_PROCESS
    if EX_Byte_Access then
      -- Duplicate the data into the MS 3 bytes
      ex_DataBus_Write_Data_i(BYTE_MSB_POS_TYPE)   <= EX_Op3(BYTE_LSB_POS_TYPE);
      ex_DataBus_Write_Data_i(BYTE_LSB_2_POS_TYPE) <= EX_Op3(BYTE_LSB_POS_TYPE);
      ex_DataBus_Write_Data_i(BYTE_LSB_1_POS_TYPE) <= EX_Op3(BYTE_LSB_POS_TYPE);
      ex_DataBus_Write_Data_i(BYTE_LSB_POS_TYPE)   <= EX_Op3(BYTE_LSB_POS_TYPE);
    elsif EX_Doublet_Access then
      -- Duplicate the data into the MS doublet
      ex_DataBus_Write_Data_i(DOUBLET_MSB_POS_TYPE) <= EX_Op3(DOUBLET_LSB_POS_TYPE);
      ex_DataBus_Write_Data_i(DOUBLET_LSB_POS_TYPE) <= EX_Op3(DOUBLET_LSB_POS_TYPE);
    else
      ex_DataBus_Write_Data_i <= EX_Op3;
    end if;
  end process Write_Data_Mirror_PROCESS;

  ----------------------------------------
  -- Byte_Enable_PROCESS
  -- Generate byte enables
  ----------------------------------------
  Byte_Enable_PROCESS : process (EX_Byte_Access, EX_Doublet_Access, ex_unaligned_Addr_2LSb) is
  begin  -- process Byte_Enable_Handler
    ex_DataBus_Byte_Enable_i <= (others => '0');  -- Default none is enabled
    if EX_Byte_Access then
      -- which byte to write
      case ex_unaligned_Addr_2LSb is
        when "00"   => ex_DataBus_Byte_Enable_i(BYTE_ENABLE_BYTE_3) <= '1';
        when "01"   => ex_DataBus_Byte_Enable_i(BYTE_ENABLE_BYTE_2) <= '1';
        when "10"   => ex_DataBus_Byte_Enable_i(BYTE_ENABLE_BYTE_1) <= '1';
        when "11"   => ex_DataBus_Byte_Enable_i(BYTE_ENABLE_BYTE_0) <= '1';
        when others => null;
      end case;
    elsif EX_Doublet_Access then
      -- which doublet to write
      case ex_unaligned_Addr_2LSb(0) is
        when '0'    => ex_DataBus_Byte_Enable_i(BYTE_ENABLE_BYTE_3 to BYTE_ENABLE_BYTE_2) <= "11";
        when '1'    => ex_DataBus_Byte_Enable_i(BYTE_ENABLE_BYTE_1 to BYTE_ENABLE_BYTE_0) <= "11";
        when others => null;
      end case;
    else
      -- Default to 32-bit write (all byte enables)
      ex_DataBus_Byte_Enable_i <= (others => '1');
    end if;
  end process Byte_Enable_PROCESS;

  EX_DataBus_Byte_Enable <= ex_DataBus_Byte_Enable_i;
  EX_DataBus_Write_Data  <= ex_DataBus_Write_Data_i;
  
  Move_To_MEM_Stage : process (Clk) is
  begin  -- process Move_To_MEM_Stage
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        MEM_DataBus_Byte_Enable <= (others => '0');
        MEM_DataBus_Write_Data  <= (others => '0');
      elsif (EX_PipeRun) then
        MEM_DataBus_Byte_Enable <= ex_DataBus_Byte_Enable_i;
        MEM_DataBus_Write_Data  <= ex_DataBus_Write_Data_i;
      end if;
    end if;
  end process Move_To_MEM_Stage;

  
  ----------------------------------------
  -- EX_DataBus_Aligned_Addr_PROCESS
  -- Provide the 2 least significant bits of the address aligned
  ----------------------------------------
  EX_DataBus_Aligned_Addr_PROCESS : process (ex_unaligned_Addr_2LSb, EX_Byte_Access, EX_Doublet_Access) is
  begin  -- process EX_DataBus_Aligned_Addr_PROCESS
    if EX_Byte_Access then
      EX_UnAlign_2LSb <= ex_unaligned_Addr_2LSb;
    elsif EX_Doublet_Access then
      EX_UnAlign_2LSb <= (ex_unaligned_Addr_2LSb(0), '0');
    else
      EX_UnAlign_2LSb <= "00";
    end if;
  end process EX_DataBus_Aligned_Addr_PROCESS;

  ----------------------------------------
  -- Steered_Read_Data_PROCESS
  -- Provide the 2 least significant bits of the address aligned
  ----------------------------------------
  -----------------------------------------------------------------------------
  -- Handle LSB
  -----------------------------------------------------------------------------
  WB_Steered_Read_Data(BYTE_LSB_POS_TYPE) <= WB_DataBus_Read_Data(Byte_MSB_POS_TYPE) when (WB_UnAlign_2LSb = "00") and WB_Byte_Access else
                                             WB_DataBus_Read_Data(Byte_LSB_2_POS_TYPE) when (((WB_UnAlign_2LSb = "01") and WB_Byte_Access) or
                                                                                             ((WB_UnAlign_2LSb(0) = '0') and WB_Doublet_Access)) else
                                             WB_DataBus_Read_Data(Byte_LSB_1_POS_TYPE) when (WB_UnAlign_2LSb = "10") and WB_Byte_Access else
                                             WB_DataBus_Read_Data(Byte_LSB_POS_TYPE);

  -----------------------------------------------------------------------------
  -- Handle LSB_1
  -----------------------------------------------------------------------------
  BYTE_LSB_1_Select: process (WB_DataBus_Read_Data, WB_UnAlign_2LSb, WB_Doublet_Access, WB_Byte_Access)
  begin  -- process BYTE_LSB_1_Select
    if WB_Byte_Access then
      WB_Steered_Read_Data(BYTE_LSB_1_POS_TYPE) <= "00000000";
    else
      if (WB_UnAlign_2LSb(0) = '0') and WB_Doublet_Access then
        WB_Steered_Read_Data(BYTE_LSB_1_POS_TYPE) <= WB_DataBus_Read_Data(Byte_MSB_POS_TYPE);
      else
        WB_Steered_Read_Data(BYTE_LSB_1_POS_TYPE) <= WB_DataBus_Read_Data(Byte_LSB_1_POS_TYPE);
      end if;
    end if;
  end process BYTE_LSB_1_Select;
    
  -----------------------------------------------------------------------------
  -- Handle MSB and LSB_2
  -----------------------------------------------------------------------------
  WB_Steered_Read_Data(DOUBLET_MSB_POS_TYPE) <= "0000000000000000" when WB_Doublet_Access or WB_Byte_Access else
                                             WB_DataBus_Read_Data(DOUBLET_MSB_POS_TYPE);

end architecture IMP;