mmu_tlb.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: mmu_tlb.vhd,v 1.2 2007/10/23 11:00:32 stefana Exp $
-------------------------------------------------------------------------------
-- mmu_tlb.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2006 by Xilinx, Inc. All rights reserved.               **
--  **                                                                       **
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--  **  information of Xilinx, Inc. , is distributed by                      **
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--  **  of a valid license agreement with Xilinx, Inc.                       **
--  **                                                                       **
--  **  Unmodified source code is guaranteed to place and route,             **
--  **  function and run at speed according to the datasheet                 **
--  **  specification. Source code is provided "as-is", with no              **
--  **  obligation on the part of Xilinx to provide support.                 **
--  **                                                                       **
--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
--  **                                                                       **
--  **  The Xilinx Support Hotline does not have access to source            **
--  **  code and therefore cannot answer specific questions related          **
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--  **  to confirm the problem in the Netlist version of the core.           **
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--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        mmu_tlb.vhd
--
-- Description:     This file contains an implementation of a Memory Management
--                  Unit Translation Look-aside Buffer, using a fully
--                  associative memory.
--
-- VHDL-Standard:   VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:   
--              mmu_tlb.vhd
--
-------------------------------------------------------------------------------
-- Author:          stefana
-- Revision:        $Revision: 1.2 $
-- Date:            $Date: 2007/10/23 11:00:32 $
--
-- History:
--   stefana 2006-10-23    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

-- pragma xilinx_rtl_off
library unisim;
use unisim.vcomponents.all;
-- pragma xilinx_rtl_on
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;
use Microblaze_v7_10_a.MMU_Types.all;

entity MMU_TLB is
  generic (
    C_TARGET      : TARGET_FAMILY_TYPE;
    C_TLBHI_WIDTH : natural := 34;         -- 34 excluding E, U0 bit
    C_ADDR_WIDTH  : natural range 0 to 3;  -- 2**0=1, 2**1=2, 2**2=4, 2**3=8
    C_STORE_TID   : boolean := true;
    C_STORE_EX    : boolean := true;
    C_STORE_WR    : boolean := true;
    C_MMU_ZONES   : integer := 16;
    C_STORE_G     : boolean := true
  );
  port (
    CLK        : in  std_logic;
    EN         : in  std_logic;

    TLB_Inval  : in  boolean;
    TLB_ADDR   : in  natural;
    TLBLO_WE   : in  std_logic;
    TLBLO_IN   : in  DATA_TYPE;
    TLBHI_WE   : in  std_logic;
    TLBHI_IN   : in  std_logic_vector(0 to C_TLBHI_WIDTH-1);

    DATA_ADDR  : in  std_logic_vector(0 to C_TLBHI_WIDTH - 5); -- TAG, TID
    HIT_EN     : in  std_logic;
    SIZE_OUT   : out SIZE_Type;
    DATALO_OUT : out DATA_TYPE;
    DATA_HIT   : out std_logic
  );
end entity MMU_TLB;

library IEEE;
use IEEE.numeric_std.to_integer;
use IEEE.numeric_std.unsigned;

architecture IMP of MMU_TLB is

  component carry_compare is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE;
      Size     : natural);
    port (
      A_Vec     : in  std_logic_vector(0 to Size-1);
      B_Vec     : in  std_logic_vector(0 to Size-1);
      Carry_In  : in  std_logic;
      Carry_Out : out std_logic);
  end component carry_compare;
  
  component carry_compare_mask is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE;
      Size     : natural);
    port (
      A_Vec     : in  std_logic_vector(0 to Size-1);
      B_Vec     : in  std_logic_vector(0 to Size-1);
      Mask      : in  std_logic_vector(0 to Size-1);
      Carry_In  : in  std_logic;
      Carry_Out : out std_logic);
  end component carry_compare_mask;

  constant C_EXTRA_INPUT_FOR_LUT6 : boolean := C_TARGET = VIRTEX5;

  -- Modes:
  --   Random access write
  --   Associative read (uses SIZE and V during lookup):
  --     Address is: TAG 0 to 21. TID 26 to 33 (unless not stored)
  --     Data is: TLBLO 0 to 31, excluding W, M, G

  subtype Addr_type is integer range 0 to 2**C_ADDR_WIDTH - 1;

  type Width_Type is array (boolean) of integer;

  -- TLBLO constants and types: RPN (22), EX (if C_STORE_EX),
  -- WR (if C_STORE_WR), ZSEL (log2 C_MMU_ZONES), I, G (if C_STORE_G)
  constant C_BIT_WIDTH   : Width_Type := (false => 0, true => 1);
  constant C_EX_WIDTH    : integer := C_BIT_WIDTH(C_STORE_EX);
  constant C_WR_WIDTH    : integer := C_BIT_WIDTH(C_STORE_WR);
  constant C_ZSEL_WIDTH  : integer := log2(C_MMU_ZONES);
  constant C_G_WIDTH     : integer := C_BIT_WIDTH(C_STORE_G);

  constant C_TLBLO_STORE_WIDTH : integer := C_EX + C_EX_WIDTH + C_WR_WIDTH +
                                            C_ZSEL_WIDTH + 1 + C_G_WIDTH;
  subtype TLBLO_Entry_Type is std_logic_vector(0 to C_TLBLO_STORE_WIDTH - 1);

  type TLBLO_Type is array (0 to 2**C_ADDR_WIDTH - 1) of TLBLO_Entry_Type;

  constant C_G_OFFSET    : integer := C_TLBLO_STORE_WIDTH - 1;
  constant C_I_OFFSET    : integer := C_G_OFFSET          - C_G_WIDTH;
  constant C_ZSEL_OFFSET : integer := C_I_OFFSET          - C_ZSEL_WIDTH;
  constant C_WR_OFFSET   : integer := C_ZSEL_OFFSET       - C_WR_WIDTH;
  constant C_EX_OFFSET   : integer := C_WR_OFFSET         - C_EX_WIDTH;


  -- TLBHI constants and types
  -- If not C_STORE_TID: TAG (22), SIZE (3), V
  -- If C_STORE_TID:     TAG (22), SIZE (3), V, TID (8), TID0
  constant C_TLBHI_STORE_WIDTH : Width_Type := (false => 26, true => 35);
  subtype TLBHI_Entry_Type is
    std_logic_vector(0 to C_TLBHI_STORE_WIDTH(C_STORE_TID) - 1);

  constant C_TAG_TID_WIDTH : Width_Type := (false => 22, true => 30);
  subtype TAG_TID_Type is
    std_logic_vector(0 to C_TAG_TID_WIDTH(C_STORE_TID) - 1);
  subtype TID_Mask_Type is std_logic_vector(22 to 29); -- TID in TAG_TID

  subtype  TID_Type is std_logic_vector(26 to 33); -- Is really bits 28 to 35
  constant C_TID_0  : integer := 34;               -- Extra bit set when TID=0

  type TLBHI_Type is array (0 to 2**C_ADDR_WIDTH - 1) of TLBHI_Entry_Type;

  -- Signals
  signal Hit        : boolean;
  signal HitAddr    : Addr_Type;
  signal TLBLO_Data : TLBLO_Entry_Type;
  signal TLBLO_Out  : TLBLO_Entry_Type;
  signal TLBHI      : TLBHI_Type;

  signal shadow_hit : std_logic_vector(Addr_type);

begin  -- architecture IMP

  -- Random access write
  TLBHI_RandomAccess_Write : process(CLK)
    variable TID_0       : std_logic;        -- Set if TID is 0
    variable TLBHI_Entry : TLBHI_Entry_Type; -- TLBHI Entry
  begin
    if CLK'event and CLK = '1' then
      if TLB_Inval then
        -- Invalidate by setting V to zero in all entries
        for I in TLBHI_Type'range loop
          TLBHI(I)(C_VALID) <= '0';
        end loop;
      elsif EN = '1' and TLBHI_WE = '1' then
        if C_STORE_TID then
          -- Set the TID_0 bit if TID is 0
          if TLBHI_IN(TID_Type'range) = (TID_Type'range => '0') then
            TID_0 := '1';
          else
            TID_0 := '0';
          end if;
          TLBHI_Entry := TLBHI_IN & TID_0;
        else
          TLBHI_Entry := TLBHI_IN(TLBHI_Entry_Type'range);
        end if;
        TLBHI(TLB_ADDR) <= TLBHI_Entry;
      end if;
    end if;
  end process TLBHI_RandomAccess_Write;

  -- Associative read
  Lookup_Shadow_Reg : for I in Addr_type generate
    signal AddrMask         : TAG_TID_Type;  -- Address mask
    signal Masked_DATA_ADDR : TAG_TID_Type;  -- Masked address
    signal Size             : SIZE_Type;     -- Entry size
    signal TAG_TID          : TAG_TID_Type;  -- Entry TAG+TID (if stored)
    signal valid            : std_logic;