mux4.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: mux4.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- mux4.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
--  **                                                                       **
--  **  This text contains proprietary, confidential                         **
--  **  information of Xilinx, Inc. , is distributed by                      **
--  **  under license from Xilinx, Inc., and may be used,                    **
--  **  copied and/or disclosed only pursuant to the terms                   **
--  **  of a valid license agreement with Xilinx, Inc.                       **
--  **                                                                       **
--  **  Unmodified source code is guaranteed to place and route,             **
--  **  function and run at speed according to the datasheet                 **
--  **  specification. Source code is provided "as-is", with no              **
--  **  obligation on the part of Xilinx to provide support.                 **
--  **                                                                       **
--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
--  **                                                                       **
--  **  The Xilinx Support Hotline does not have access to source            **
--  **  code and therefore cannot answer specific questions related          **
--  **  to source HDL. The Xilinx Support Hotline will only be able          **
--  **  to confirm the problem in the Netlist version of the core.           **
--  **                                                                       **
--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        mux4.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              mux4.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2003-11-26    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;

entity mux4 is
  generic (
    D_Size : natural);
  port (
    A        : in   std_logic_vector(0 to D_Size-1);
    B        : in   std_logic_vector(0 to D_Size-1);
    C        : in   std_logic_vector(0 to D_Size-1);
    D        : in   std_logic_vector(0 to D_Size-1);
    Sel      : in   std_logic_vector(0 to 1);
    Res      : out  std_logic_vector(0 to D_Size-1)
    );  
end entity mux4;

-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------

architecture IMP of mux4 is
  
  component MUXF5 is
     port (
       O : out std_logic;
       I0 : in std_logic;
       I1 : in std_logic;
       S : in std_logic
     );
   end component MUXF5;

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------

  signal S1 : std_logic_vector(0 to D_Size-1);
  signal S2 : std_logic_vector(0 to D_Size-1);
begin  -- architecture imp

  The_Mux : for I in 0 to D_Size-1 generate
    S1(I) <= A(I) when Sel(1) = '0' else B(I);
    S2(I) <= C(I) when Sel(1) = '0' else D(I);
    MUXF5_I1 : MUXF5
      port map (
        O  => Res(I),                   -- [out std_logic]
        I0 => S1(I),                    -- [in  std_logic]
        I1 => S2(I),                    -- [in  std_logic]
        S  => Sel(0));                    -- [in std_logic]

  end generate The_Mux;
end architecture IMP;