icache.vhd

来自「Xilinx软核microblaze源码(VHDL)版本7.10」· VHDL 代码 · 共 916 行 · 第 1/3 页

                 (not(Instr_Addr_1(29)) and tag_bits(2)));
  
        Word_Valid_MUXCY_1 : MUXCY_L
          port map (
            DI => '0',                        -- [in  std_logic]
            CI => tag_ok,
            S  => Sel1,                       -- [in  std_logic]
            LO => carry);                     -- [out std_logic]
  
        -- Instr_Addr_1(28 to 29) = "01" <=> tag_bits(1)
        -- Instr_Addr_1(28 to 29) = "00" <=> tag_bits(0)
        Sel2 <= Instr_Addr_1(28) or
                ((Instr_Addr_1(29) and tag_bits(1)) or
                 (not(Instr_Addr_1(29)) and tag_bits(0)));
  
        Word_Valid_MUXCY_2 : MUXCY_L
          port map (
            DI => '0',                        -- [in  std_logic]
            CI => carry,
            S  => Sel2,                       -- [in  std_logic]
            LO => word_is_valid);             -- [out std_logic]
  
      end generate Using_4LUT;
      
      Using_6LUT : if ( C_LUT6_OPTIMIZED ) generate
        signal sel   : std_logic;
      begin
        -- Instr_Addr_1(28 to 29) = "11" <=> tag_bits(3)
        -- Instr_Addr_1(28 to 29) = "10" <=> tag_bits(2)
        -- Instr_Addr_1(28 to 29) = "01" <=> tag_bits(1)
        -- Instr_Addr_1(28 to 29) = "00" <=> tag_bits(0)
        Sel  <= tag_bits(3) when (Instr_Addr_1(28 to 29) = "11") else 
                tag_bits(2) when (Instr_Addr_1(28 to 29) = "10") else 
                tag_bits(1) when (Instr_Addr_1(28 to 29) = "01") else 
                tag_bits(0) when (Instr_Addr_1(28 to 29) = "00") else 
                '0';
        
        Lut6_Word_Valid_MUXCY : MUXCY_L
          port map (
            DI => '0',                        -- [in  std_logic]
            CI => tag_ok,
            S  => Sel,                        -- [in  std_logic]
            LO => word_is_valid);             -- [out std_logic]
  
      end generate Using_6LUT;
    end generate Using_4word_lines;

    
    combined_iready_n <= not Combined_IReady;

    Combined_IReady_MUXCY : MUXCY_L
      port map (
        DI => '1',                -- [in  std_logic]
        CI => word_is_valid,      -- [in  std_logic]
        S  => combined_iready_n,  -- [in  std_logic]
        LO => IReady_II);          -- [out std_logic]

    Using_XX_Access_Part2 : if (C_ICACHE_ALWAYS_USED /= 0) generate
      carry_or_I1 : carry_or
        generic map (
          C_TARGET => C_TARGET)         -- [TARGET_FAMILY_TYPE]
        port map (
          Carry_IN  => IReady_II,       -- [in  std_logic]
          A         => xx_valid_data,   -- [in  std_logic]
          Carry_OUT => IReady_I);       -- [out std_logic]
    end generate Using_XX_Access_Part2;

    Not_Using_XX_Access_Part2: if (C_ICACHE_ALWAYS_USED = 0) generate
     IReady_I <= IReady_II;      
    end generate Not_Using_XX_Access_Part2;


  end generate Using_FPGA_FSL_2;

  Using_RTL_FSL_2 : if C_TARGET = RTL generate

    Word_Is_Valid_Gen : process (Instr_Addr, tag_ok, tag_bits)
      variable temp_Instr_Addr : std_logic_vector(0 to CACHELINE_BITS-1);
    begin  -- process Word_Is_Valid_Gen
      temp_Instr_Addr := Instr_Addr(30-CACHELINE_BITS to 29);
      word_is_valid   <= tag_ok and tag_bits(to_integer(unsigned(temp_Instr_Addr)));
    end process Word_Is_Valid_Gen;

    IReady_I <= Combined_IReady or Word_Is_Valid;

  end generate Using_RTL_FSL_2;

  -- We have a cache hit if we have a valid_req and the cacheline is in cache
  -- and the word is valid
  -- Needs more complicated expression to handle when caches is being
  -- disabled and one last req is underway.
  -- Cache_Hit <= valid_req and Tag_Hit and Word_Is_Valid;

  IReady <= IReady_I;

  -- Do a FSL request when we have a valid request but the cacheline is not
  -- in cache
  ICACHE_FSL_Out_Write_i <= Valid_Req_1st_Cycle_XX and not Tag_ok when not reset else '0';
  ICACHE_FSL_OUT_Write   <= ICACHE_FSL_Out_Write_i;
  ICACHE_FSL_OUT_Data    <= Instr_Addr_1;
  ICACHE_FSL_OUT_Control <= '0';  -- Only read requests
  ---------------------------------------------------------------------------
  -- 
  ---------------------------------------------------------------------------
  ICACHE_FSL_IN_Read     <= ICACHE_FSL_IN_Exists;

  Requested_Address : process (Clk) is
  begin  -- process Requested_Address
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Reset then  -- synchronous reset (active high)
        Req_Addr <= (others => '0');
      elsif ((Valid_req_1st_cycle and not Tag_Ok) = '1') then
        Req_Addr <= Instr_Addr_1;
      end if;
    end if;
  end process Requested_Address;

  CacheLine_Counter : process (Clk) is
  begin  -- process CacheLine_Counter
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Reset then  -- synchronous reset (active high)
        CacheLine_Cnt <= (others => '0');
      elsif (ICACHE_FSL_IN_Exists = '1') then
        CacheLine_Cnt <= std_logic_vector(unsigned(CacheLine_Cnt) + 1);
      end if;
    end if;
  end process CacheLine_Counter;

  CacheLine_Counter2 : process (Clk) is
  begin  -- process CacheLine_Counter2
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Reset then  -- synchronous reset (active high)
        CacheLine_Cnt2 <= (others => '0');
      else
        if (Update_Idle = '1') then
          CacheLine_Cnt2 <= Req_Addr(30 - CACHELINE_BITS to 29);
        elsif (ICACHE_FSL_IN_Exists = '1') then
          CacheLine_Cnt2 <= std_logic_vector(unsigned(CacheLine_Cnt2) + 1);
        end if;
      end if;
    end if;
  end process CacheLine_Counter2;

  Update_Idle <= '1' when (CacheLine_Cnt = CacheLine_Cnt_Low and ICACHE_FSL_IN_Exists = '0') or
                 (CacheLine_Cnt = CacheLine_Cnt_High and ICACHE_FSL_IN_Exists = '1')
                 else '0';

  ICache_Read_Idle_DFF : process (Clk) is
    variable Update_Idle_1          : std_logic;
    variable ICACHE_FSL_OUT_Write_1 : std_logic;
  begin  -- process ICache_Read_Idle_DFF
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Reset then                  -- synchronous reset (active high)
        ICache_Read_Idle       <= true;
        Update_Idle_1          := '1';
        ICACHE_FSL_OUT_Write_1 := ICACHE_FSL_OUT_Write_i;
      else
        if ICACHE_FSL_OUT_Write_1 = '1' then
          ICache_Read_Idle <= false;  -- FSL access started
        elsif (Update_Idle_1 = '0') and (Update_Idle = '1') then
          ICache_Read_Idle <= true;  -- FSL access ended
        end if;
        ICACHE_FSL_OUT_Write_1 := ICACHE_FSL_OUT_Write_i;
        Update_Idle_1          := Update_Idle;
      end if;
    end if;
  end process ICache_Read_Idle_DFF;

  New_Tag_Addr_DFF : process (Clk) is
  begin  -- process New_Tag_Addr_DFF
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Update_Idle = '1' then
        New_Tag_Addr <= Req_Addr(30 - CACHELINE_BITS - Tag_Addr_Size
                                 to 29-CACHELINE_BITS);
        Addr_Tag_Bits <= Req_Addr(30 - CACHELINE_BITS - Tag_Addr_Size - NO_ADDR_TAG_BITS
                                  to 29 - CACHELINE_BITS - Tag_Addr_Size);
      end if;
    end if;
  end process New_Tag_Addr_DFF;

  -- Calculate the valid bits that will be written during a cacheline update
  Valid_Bits_Handle : process (Clk) is
    variable tmp : std_logic_vector(valid_Bits'range);
  begin  -- process Valid_Bits_Handle
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Update_Idle = '1' then         -- synchronous reset (active high)
        valid_Bits                                                          <= (others => '0');
        valid_Bits(to_integer(unsigned(req_Addr(30-CACHELINE_BITS to 29)))) <= '1';
      elsif (ICACHE_FSL_IN_Exists = '1') then
        tmp(1 to tmp'right) := valid_Bits(0 to valid_Bits'right-1);
        tmp(0)              := valid_Bits(valid_Bits'right);
        valid_Bits          <= tmp or valid_Bits;
      end if;
    end if;
  end process Valid_Bits_Handle;

  New_Tag_Bits_Gen : process(ICACHE_FSL_IN_Exists, Real_Valid_Bits, Addr_Tag_Bits) is
  begin  -- process New_Tag_Bits_Gen
    new_tag_bits <= (others => '0');
    if ICACHE_FSL_IN_Exists = '1' then
      new_tag_bits(C_CACHELINE_SIZE) <= '1';  -- Always write in a valid tag        
    else
      new_tag_bits(C_CACHELINE_SIZE) <= '0';
    end if;
    new_tag_bits(0 to C_CACHELINE_SIZE-1)                                     <= Real_Valid_Bits;
    new_tag_bits(1 + C_CACHELINE_SIZE to C_CACHELINE_SIZE + NO_ADDR_TAG_BITS) <= Addr_Tag_Bits;
  end process New_Tag_Bits_Gen;

  write_cache    <= '1' when (Write_ICache) else ICACHE_FSL_IN_Exists and cache_updated_allowed;
  write_cache_be <= (others => write_cache);

  Real_Valid_Bits <= Valid_Bits when ICACHE_FSL_IN_Exists = '1' else All_False_Bits;

  Real_New_Tag_Addr <= New_Tag_Addr when ICACHE_FSL_IN_Exists = '1' else
                       Op1(30 - CACHELINE_BITS - Tag_Addr_Size
                           to 29-CACHELINE_BITS);
  ---------------------------------------------------------------------------
  -- The tag memory
  ---------------------------------------------------------------------------
  Tag_Memory : RAM_Module
    generic map (
      C_TARGET     => C_TARGET,  -- [TARGET_FAMILY_TYPE]
      C_DATA_WIDTH => Tag_Word_Size,  -- [natural range 1 to 36]
      C_ADDR_WIDTH => Tag_Addr_Size,  -- [natural range 1 to 14]
      C_FORCE_BRAM => Tag_Force_BRAM)  -- [boolean]
    port map (
                                        -- PORT A
      CLKA      => CLK,  -- [in  std_logic]
      WEA       => null4,  -- [in  std_logic_vector(0 to 3)] Assume byte write handling
      ENA       => bram_enable,  -- [in  std_logic]
      ADDRA     => tag_addr_lookup,  -- [in  std_logic_vector(0 to C_ADDR_WIDTH-1)]
      DATA_INA  => null_tag_data,  -- [in  std_logic_vector(0 to C_DATA_WIDTH-1)]
      DATA_OUTA => tag_bits,  -- [out std_logic_vector(0 to C_DATA_WIDTH-1)]
                                    -- PORT B
      CLKB      => CLK,  -- [in  std_logic]
      WEB       => write_cache_be,  -- [in  std_logic_vector(0 to 3)] Assume byte write handling
      ENB       => '1',  -- [in  std_logic]
      ADDRB     => Real_New_Tag_Addr,  -- [in  std_logic_vector(0 to C_ADDR_WIDTH-1)]
      DATA_INB  => new_tag_bits,  -- [in  std_logic_vector(0 to C_DATA_WIDTH-1)]
      DATA_OUTB => open);  -- [out std_logic_vector(0 to C_DATA_WIDTH-1)]

  tag_addr_lookup <= True_Instr_Addr(30 - CACHELINE_BITS - Tag_Addr_Size
                                     to 29-CACHELINE_BITS);

  ---------------------------------------------------------------------------
  -- Then the Data memory
  ---------------------------------------------------------------------------

  New_Data_Addr_DFF : process (Clk) is
  begin  -- process New_Data_Addr_DFF
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Update_Idle = '1' then
        New_Data_Addr1 <= Req_Addr(30-Data_Addr_Size to 29-CACHELINE_BITS);
      end if;
    end if;
  end process New_Data_Addr_DFF;

  new_data_addr <= New_Data_Addr1 & Cacheline_Cnt2;

  data_addr_lookup <= True_Instr_Addr(30-Data_Addr_Size to 29);

  data_cache_write <= (others => ICACHE_FSL_IN_Exists and cache_updated_allowed);

  Data_Memory : RAM_Module
    generic map (
      C_TARGET     => C_TARGET,  -- [TARGET_FAMILY_TYPE]
      C_DATA_WIDTH => 32,  -- [natural range 1 to 36]
      C_ADDR_WIDTH => Data_Addr_Size,  -- [natural range 1 to 14]
      C_FORCE_BRAM => false)  -- [boolean]
    port map (
                                        -- PORT A
      CLKA      => Clk,  -- [in  std_logic]
      WEA       => (others => '0'),  -- [in  std_logic_vector(0 to 3)] Assume byte write handling
      ENA       => bram_enable,  -- [in  std_logic]
      ADDRA     => data_addr_lookup,  -- [in  std_logic_vector(0 to C_ADDR_WIDTH-1)]
      DATA_INA  => null_data_data,  -- [in  std_logic_vector(0 to C_DATA_WIDTH-1)]
      DATA_OUTA => instr_i,  -- [out std_logic_vector(0 to C_DATA_WIDTH-1)]
                                   -- PORT B
      CLKB      => Clk,  -- [in  std_logic]
      WEB       => data_cache_write,  -- [in  std_logic_vector(0 to 3)] Assume byte write handling
      ENB       => bram_enable,  -- [in  std_logic]
      ADDRB     => new_data_addr,  -- [in  std_logic_vector(0 to C_ADDR_WIDTH-1)]
      DATA_INB  => ICACHE_FSL_IN_Data,  -- [in  std_logic_vector(0 to C_DATA_WIDTH-1)]
      DATA_OUTB => open);  -- [out std_logic_vector(0 to C_DATA_WIDTH-1)]

  Instr <= Instr_I when xx_valid_data = '0' else xx_data;

  Trace_DFF : process (Clk) is
  begin  -- process Trace_DFF
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Reset then  -- synchronous reset (active true)
        Trace_Cache_Hit <= '0';
        Trace_Cache_Req <= '0';
      else
        Trace_Cache_Hit <= Word_Is_Valid;
        Trace_Cache_Req <= valid_req_1st_cycle;
      end if;
    end if;
  end process Trace_DFF;


end architecture IMP;