div_unit.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

    Diff_AddSub : for I in C_DATA_SIZE downto 0 generate
      Diff_Sel(I) <= R(I) xor D(I) xor next_sub;                

      Diff_MUXCY_L : MUXCY_L
        port map (
          DI => R(I),                   -- [in  std_logic]
          CI => Diff_Carry(I+1),        -- [in  std_logic]
          S  => Diff_Sel(I),            -- [in  std_logic]
          LO => Diff_Carry(I));         -- [out std_logic]

      Diff_XORCY : XORCY
        port map (
          LI => Diff_Sel(I),            -- [in  std_logic]
          CI => Diff_Carry(I+1),        -- [in  std_logic]
          O  => Diff(I));               -- [out std_logic]
    end generate Diff_AddSub;

--   Res_Neg <= diff(diff'left);
    Res_Neg <= not Diff(0);

--   diff <= std_logic_vector(unsigned(R) - unsigned(D)) when next_sub = '1' else
--          std_logic_vector(unsigned(R) + unsigned(D));

    div_result_is_zero <= Reg_Zero;

    reset_Q <= '1' when reset else div_result_is_zero or Not_Div_Op;

    -----------------------------------------------------------------------------
    -- Create the logic for New_Q
    --
    -- Oper  New_Q          Start_Div  Op2(MSB) Last_Cycle Sign
    --  00   Op2                 1        0         -       -
    --  01   not(Op2) + 1        1        1         -       -
    --  10   Q << 1              0        -         1       0
    --  11   not(Q<<1) + 1       0        -         1       1
    --
    -- Start_Div  Op2(MSB) Last_Cycle Sign Div_Count    Oper
    --     1        0         -       -       -          00
    --     1        1         -       -       -          01
    --     0        -         1       0       -          10
    --     0        -         1       1       -          11
    --     0        -         0       -       1          10
    --
    --
    --                    Op2, Q
    --  Use_Op2,Invert  00 01 11 10
    --          00       0  1  1  0 = 1010
    --          01       1  0  0  1 = 0101
    --          11       1  1  0  0 = 0011
    --          10       0  0  1  1 = 1100
    -- INIT = 0011 1100 0101 1010 = 3C5A
    -----------------------------------------------------------------------------

    New_Q(C_DATA_SIZE) <= Div_Count and Res_Neg;

    New_Q_Carry(C_DATA_SIZE) <= (not Unsigned_op) and
                                ((Start_Div and op2(op2'left)) or
                                 (Last_Cycle and Sign));

    New_Q_Use_Op2 <= Start_Div;
    New_Q_Invert  <= New_Q_Carry(C_DATA_SIZE);

    New_Q_Handle : for I in C_DATA_SIZE-1 downto 0 generate
      -- New_Q_Sel(I) <= Op2(I) xor New_Q_Invert when New_Q_Use_Op2 = '1' else Q(I+1) xor New_Q_Invert;

      New_Q_LUT4: LUT4
        generic map (
          INIT => X"3C5A")                 -- [bit_vector]
        port map (
          O  => New_Q_Sel(I),                      -- [out std_logic]
          I0 => Q(I+1),                     -- [in  std_logic]
          I1 => Op2(I),                     -- [in  std_logic]
          I2 => New_Q_Invert,                     -- [in  std_logic]
          I3 => New_Q_Use_Op2);                    -- [in std_logic]
      

      New_Q_MUXCY_L : MUXCY_L
        port map (
          DI => '0',                    -- [in  std_logic]
          CI => New_Q_Carry(I+1),       -- [in  std_logic]
          S  => New_Q_Sel(I),           -- [in  std_logic]
          LO => New_Q_Carry(I));        -- [out std_logic]

      New_Q_XORCY : XORCY
        port map (
          LI => New_Q_Sel(I),           -- [in  std_logic]
          CI => New_Q_Carry(I+1),       -- [in  std_logic]
          O  => New_Q(I));              -- [out std_logic]
    end generate New_Q_Handle;

--  Handle_new_Q : process (Start_Div, Q, Op2, Div_Count, Res_Neg, Last_Cycle, Sign) is
--  begin  -- process Handle_new_Q
--    new_Q <= Q;
--    if (Start_Div = '1') then
--      if (Op2(Op2'left) = '1') then
--        new_Q(new_Q'left to new_Q'right-1) <= std_logic_vector(unsigned(not Op2) + 1);
--        new_Q(new_Q'right)                 <= '0';
--      else
--        new_Q <= Op2 & '0';
--      end if;
--    elsif (Last_Cycle = '1') then
--      if (sign = '1') then
--        new_Q(new_Q'left to new_Q'right-1) <= std_logic_vector(unsigned(not Q(Q'left+1 to Q'right)) + 1);
--        new_Q(new_Q'right) <= '0';
--      else
--        new_Q(new_Q'left to new_Q'right-1) <= Q(Q'left+1 to Q'right);
--        new_Q(new_Q'right) <= '0';        
--      end if;
--    elsif (Div_Count = '1') then
--      new_Q <= Q(Q'left+1 to Q'right) & Res_Neg;
--    end if;
--  end process Handle_new_Q;

    Handle_Q : process (Clk) is
    begin  -- process Handle_Q
      if Clk'event and Clk = '1' then   -- rising clock edge
        if (Reset_Q = '1') then
          Q <= (others => '0');
        elsif (Div_Count = '1') or (Start_Div = '1') then
          Q <= new_Q(new_Q'left to new_Q'right);
        end if;
      end if;
    end process Handle_Q;

    Div_Result <= Q(Q'left to Q'right-1);

    Handle_R : process (Clk) is
    begin  -- process Handle_R
      if Clk'event and Clk = '1' then   -- rising clock edge
        if (Start_Div = '1') then
          R          <= (others => '0');
          R(R'right) <= new_Q(new_Q'left);
        elsif (div_count = '1') then
          R <= Diff(Diff'left+1 to Diff'right) & new_Q(new_Q'left);
        end if;
      end if;
    end process Handle_R;

    
    D_Carry(C_DATA_SIZE) <= Op1(Op1'left) and not Unsigned_op;

    D_Handle: for I in C_DATA_SIZE-1 downto 0 generate

      D_Sel(I) <= Op1(I) xor (Op1(Op1'left) and not Unsigned_op);

      D_MUXCY_L : MUXCY_L
        port map (
          DI => '0',                    -- [in  std_logic]
          CI => D_Carry(I+1),       -- [in  std_logic]
          S  => D_Sel(I),           -- [in  std_logic]
          LO => D_Carry(I));        -- [out std_logic]

      D_XORCY : XORCY
        port map (
          LI => D_Sel(I),           -- [in  std_logic]
          CI => D_Carry(I+1),       -- [in  std_logic]
          O  => D_I(I));              -- [out std_logic]
      
    end generate D_Handle;
    
    Handle_D : process (Clk) is
    begin  -- process Handle_D
      if Clk'event and Clk = '1' then   -- rising clock edge
        if (Start_Div = '1') then
          D <= '0' & D_I;
        end if;
      end if;
    end process Handle_D;

    Next_Sub_DFF : process (Clk) is
    begin  -- process Next_Sub_DFF
      if Clk'event and Clk = '1' then  -- rising clock edge
        if Reset then
          next_sub <= '1';
        else
          if (Start_Div = '1') then
            next_sub <= '1';
          elsif (div_count = '1') then
            next_sub <= not diff(diff'left);
          end if;
        end if;
      end if;
    end process Next_Sub_DFF;

    Start_Div_SRL16E_1 : SRL16E
      port map (
        Q   => Start_Div_16,            -- [out std_logic]
        A0  => '1',                     -- [in  std_logic]
        A1  => '1',                     -- [in  std_logic]
        A2  => '1',                     -- [in  std_logic]
        A3  => '1',                     -- [in  std_logic]
        CE  => '1',                     -- [in  std_logic]
        Clk => Clk,                     -- [in  std_logic]
        D   => Start_Div_1);            -- [in std_logic]

    Start_Div_SRL16E_2 : SRL16E
      port map (
        Q   => Start_Div_31,            -- [out std_logic]
        A0  => '0',                     -- [in  std_logic]
        A1  => '1',                     -- [in  std_logic]
        A2  => '1',                     -- [in  std_logic]
        A3  => '1',                     -- [in  std_logic]
        CE  => '1',                     -- [in  std_logic]
        Clk => Clk,                     -- [in  std_logic]
        D   => Start_Div_16);           -- [in std_logic]

    Start_div_32_dff: process (Clk) is
    begin  -- process Start_div_32_dff
      if Clk'event and Clk = '1' then  -- rising clock edge
        Start_Div_32 <= Start_Div_31;
      end if;
    end process Start_div_32_dff;
    
    Last_Cycle <= Start_Div_32;

    Div_Done_DFF: process (Clk) is
    begin  -- process Div_Done_DFF
      if Clk'event and Clk = '1' then  -- rising clock edge
        if (OF_PipeRun) or (Start_Div_32 = '1') then
          Div_Done <= '0';
        elsif (Start_Div = '1') then
          Div_Done <= Reg_Zero;
        elsif (Start_Div_31 = '1') then
          Div_Done <= '1';
        end if;
      end if;
    end process Div_Done_DFF;

    Div_Count_DFF: process (Clk) is
    begin  -- process Div_Count_DFF
      if Clk'event and Clk = '1' then  -- rising clock edge
        if (Start_Div_32 = '1') then
          Div_Count <= '0';
        elsif (Start_Div = '1') then
          Div_Count <= not Reg_Zero;
        end if;
      end if;
    end process Div_Count_DFF;

    Div_Handle : process (Clk) is
    begin  -- process Div_Handle
      if Clk'event and Clk = '1' then  -- rising clock edge
        if Reset then
          -- Index       <= 0;
          Div_By_Zero <= '0';
          Sign        <= '0';
          Start_Div_1 <= '0';
        else
          if (OF_PipeRun) then
            Div_By_Zero <= '0';
          end if;
          Start_Div_1 <= '0';
          if (Start_Div = '1') then
            if Reg_Zero = '0' then
              Start_Div_1 <= '1';
            else
              Div_By_Zero <= '1';
            end if;
            Sign <= Op2(Op2'left) xor Op1(Op1'left);
          end if;
        end if;
      end if;
    end process Div_Handle;

  end generate Using_FPGA;

end IMP;