iopb_interface.vhd

来自「Xilinx软核microblaze源码(VHDL)版本7.10」· VHDL 代码 · 共 258 行

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: iopb_interface.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- IOPB_Interface - entity/architecture
-------------------------------------------------------------------------------
--
-- ****************************************************************************
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-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc.
-- **
-- ** Unmodified source code is guaranteed to place and route,
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
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-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
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-- ** version of the core (and thus indirectly, the original core source
-- **
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-- ** This copyright and support notice must be retained as part
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-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        iopb_interface.vhd
-- Description:     Instruction side OPB interface for MicroBlaze
--
-------------------------------------------------------------------------------
-- Structure: 
--
--              iopb_interface.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY>_I#|<FUNC>" , "<ENTITY>_I"
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                                -- instruction fetch
--    OF                                -- operand fetch
--    EX                                -- execute
--    MEM                               -- memory
--    WB                                -- write back
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity IOPB_Interface is
  generic (
    C_OPB_WIDTH :    natural := 32
    );
  port (
    -- global signals
    Clk         : in std_logic;
    Reset       : in std_logic;

    -- OPB signals
    IM_ABus      : out std_logic_vector(0 to C_OPB_WIDTH-1);
    IM_BE        : out std_logic_vector(0 to (C_OPB_WIDTH-1)/8);
    IM_busLock   : out std_logic;
    IM_request   : out std_logic;
    IM_select    : out std_logic;
    IM_seqAddr   : out std_logic;
    IM_DBus      : out std_logic_vector(0 to C_OPB_WIDTH-1);
    IM_RNW       : out std_logic;
    IOPB_DBus    : in  std_logic_vector(0 to C_OPB_WIDTH-1);
    IOPB_errAck  : in  std_logic;
    IOPB_MGrant  : in  std_logic;
    IOPB_retry   : in  std_logic;
    IOPB_timeout : in  std_logic;
    IOPB_xferAck : in  std_logic;

    -- Local Bus signals
    IOPB_Data_Strobe  : out std_logic;
    IOPB_Data         : out DATA_TYPE;
    IB_Addr           : in  DATA_TYPE;
    IB_Addr_Strobe    : in  std_logic;
    IB_Fetch          : in  std_logic;
    IOPB_Drop_Request : in  std_logic;

    -- other signals
    IOPB_Exception     : out std_logic
    );

end entity IOPB_Interface;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of IOPB_Interface is

  signal valid_retry    : std_logic;
  signal valid_retry_d1 : std_logic;
  signal valid_timeout  : std_logic;
  signal valid_errAck   : std_logic;
  signal valid_xferAck  : std_logic;

  signal request_hold         : std_logic;
  signal valid_acknowledge    : std_logic;
  signal terminate_access     : std_logic;
  signal access_error         : std_logic;
  signal instr_bus_access     : std_logic;
  signal ib_addr_strobe_d1    : std_logic;
  signal iM_select_i          : std_logic;
  signal instr_addr           : DATA_TYPE;
  signal iM_request_i         : std_logic;
  signal requested_grant      : std_logic;
  signal mem_access_completed : std_logic;

begin
  -----------------------------------------------------------------------------
  -- Unused signals
  -----------------------------------------------------------------------------
  -- sequentioal addressing not used by MicroBlaze
  IM_seqAddr <= '0';
  -- bus locking not used on instruction side
  IM_busLock <= '0';
  -- No write on Instuction side
  IM_DBus    <= (others => '0');

  -----------------------------------------------------------------------------
  -- Qualify handshake signals valid for this master
  -----------------------------------------------------------------------------
  valid_retry   <= iM_select_i and IOPB_retry;
  valid_timeout <= iM_select_i and IOPB_timeout;
  valid_xferAck <= iM_select_i and IOPB_xferAck;
  valid_errAck  <= iM_select_i and IOPB_errAck;

  -----------------------------------------------------------------------------
  -- Arbitration signalling
  -----------------------------------------------------------------------------  
  iM_request_i    <= instr_bus_access and
                     not IOPB_Drop_Request and  -- No request if it's cache or lmb
                     not iM_select_i and  -- Remove once granted the bus
                     not valid_retry_d1  -- remove temporarily for a retry
                     and not mem_access_completed;  -- Inhibit invalid reqyest at the
                                        -- last cycle of an access
  IM_request      <= iM_request_i;
  requested_grant <= IOPB_MGrant and iM_request_i;

  valid_acknowledge <= valid_xferAck or valid_retry;
  terminate_access  <= valid_acknowledge or valid_timeout or valid_errAck;

  -----------------------------------------------------------------------------
  -- Capture internal instruction bus
  -----------------------------------------------------------------------------
  Capture_IBus : process (Clk)
  begin  -- process Capture_IBus
    if Clk'event and Clk = '1' then     -- rising clock edge
      ib_addr_strobe_d1 <= IB_Addr_Strobe;
      if IB_Addr_Strobe = '1' then
        instr_addr      <= IB_Addr;
      end if;
    end if;
  end process Capture_IBus;

  Request_Hold_DFF : process (clk)
  begin  -- process Request_Hold_DFF
    if clk'event and clk = '1' then     -- rising clock edge
      -- An access for the IOPB since neither XCL or LMB has requested a drop
      if ib_addr_strobe_d1 = '1' and IOPB_Drop_Request = '0' then
        request_hold <= '1';
      end if;
      -- Remove the hold when an access is finished
      if (valid_xferAck = '1') or (access_error = '1') or (reset = '1') then
        request_hold <= '0';
      end if;
    end if;
  end process Request_Hold_DFF;

  -- An access is either the first cycle or the hold signal
  instr_bus_access <= ib_addr_strobe_d1 or request_hold;

  IM_Select <= iM_select_i;

  -----------------------------------------------------------------------------
  -- Address and byte enable
  -----------------------------------------------------------------------------
  address_DFF : process (clk)
  begin
    if clk'event and clk = '1' then     -- rising clock edge
      if Reset = '1' or terminate_access = '1' then
        IM_ABus       <= (others => '0');
        IM_RNW        <= '0';
        IM_BE         <= (others => '0');
        iM_select_i   <= '0';
      else
        if requested_grant = '1' then
          IM_ABus     <= instr_addr;
          IM_RNW      <= '1';
          IM_BE       <= (others => '1');
          iM_select_i <= '1';
        end if;
      end if;
    end if;
  end process address_DFF;

  -----------------------------------------------------------------------------
  -- Instruction OPB access completion
  -----------------------------------------------------------------------------
  access_error <= valid_errAck or (valid_timeout and not valid_acknowledge);

  IOPB_Data_Strobe <= mem_access_completed;

  access_completion_DFF : process (Clk)
  begin
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then
        IOPB_Data            <= (others => '0');
        IOPB_Exception       <= '0';
        valid_retry_d1       <= '0';
        mem_access_completed <= '0';
      else
        valid_retry_d1       <= valid_retry;
        mem_access_completed <= valid_xferAck or access_error;
        IOPB_Exception       <= access_error;
        IOPB_Data            <= IOPB_DBus;
      end if;
    end if;
  end process access_completion_DFF;

end architecture IMP;