fpu_conv.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

            temp_shift    := std_logic_vector("10010110" - unsigned(fconv_op_1(1 to 8)));
            shift         <= temp_shift(4 to 8);
          else
            left_shifting <= true;
--            shift      <= to_integer(unsigned(temp_exp)) mod 32;
            shift         <= temp_exp(4 to 8);
          end if;
        end if;
      end if;
    end if;
  end process FCONV_FSB_PROC;

  ---------------------------------------------------------------------------
  -- Need to shift the value into the right position
  ---------------------------------------------------------------------------
  left_right_shifter : block is
    subtype shift_type is std_logic_vector(0 to fconv_op_2'right);
    signal fconv_op_2_reversed : shift_type;
    signal mux1                : shift_type;
    signal mux2                : shift_type;
    signal mux3                : shift_type;
    signal mux4                : shift_type;
    signal mux4_reversed       : shift_type;
    signal void_bit            : std_logic;
    signal left_shifting_1     : boolean;
    signal shift_1             : std_logic_vector(0 to 4);
  begin  -- block left_right_shifter
    
    void_bit <= '0';                    -- Always logic shifts

    FCONV_OP_2_Rev : process (fconv_op_2) is
      variable rev : shift_type;
    begin  -- process FCONV_OP_2_Rev;
      for I in Fconv_op_2'left to Fconv_op_2'right loop
        rev(I) := Fconv_op_2(Fconv_op_2'right - I);
      end loop;  -- I
      fconv_op_2_reversed <= rev;
    end process FCONV_OP_2_Rev;

    -- Reversed Fconv_op_2 used for right shift
    mux1 <= Fconv_op_2 when Left_shifting else fconv_op_2_reversed;

    ----------------------------------------
    -- Zero_Three_Bits_Mux2
    -- This second mux selects between 0, 1, 2, and 3 bits shifted
    ----------------------------------------
    Zero_Three_Bits_Mux2 : process (mux1, shift, void_bit) is
    begin  -- process Zero_Three_Bits_Mux2
      if (shift(3 to 4) = "00") then
        -- No shifting this mux
        mux2 <= mux1;
      elsif (shift(3 to 4) = "01") then
        -- Shift 1 bit
        mux2                            <= (others => void_bit);
        mux2(mux2'left to mux2'right-1) <= mux1(mux1'left+1 to mux1'right);
      elsif (shift(3 to 4) = "10") then
        -- Shift 2 bits
        mux2                            <= (others => void_bit);
        mux2(mux2'left to mux2'right-2) <= mux1(mux1'left+2 to mux1'right);
      else                              --          "11"
        -- Shift 3 bits
        mux2                            <= (others => void_bit);
        mux2(mux2'left to mux2'right-3) <= mux1(mux1'left+3 to mux1'right);
      end if;
    end process Zero_Three_Bits_Mux2;

    ----------------------------------------
    -- Zero_Twelve_Bits_Mux3_DFF
    -- This third mux selects between 0, 4, 8, 12 bits shifter
    ----------------------------------------
    Zero_Twelve_Bits_Mux3_DFF : process (Clk) is
    begin  -- Zero_Twelve_Bits_Mux3_DFF
      if Clk'event and Clk = '1' then   -- rising clock edge
        if Reset = '1' then
          mux3            <= (others => '0');
          left_shifting_1 <= false;
          shift_1         <= (others => '0');
        else
          left_shifting_1 <= left_shifting;
          shift_1         <= shift;
          if (shift(1 to 2) = "00") then
            -- No additional shifting from this mux
            mux3 <= mux2;
          elsif (shift(1 to 2) = "01") then
            -- Shift another 4 bits
            mux3                            <= (others => void_bit);
            mux3(mux3'left to mux3'right-4) <= mux2(mux2'left+4 to mux2'right);
          elsif (shift(1 to 2) = "10") then
            -- Shift another 8 bits
            mux3                            <= (others => void_bit);
            mux3(mux3'left to mux3'right-8) <= mux2(mux2'left+8 to mux2'right);
          else                          --            "11"
            -- Shift another 12 bits
            mux3                             <= (others => void_bit);
            mux3(mux3'left to mux3'right-12) <= mux2(mux2'left+12 to mux2'right);
          end if;
        end if;
      end if;
    end process Zero_Twelve_Bits_Mux3_DFF;

    Zero_Sixteen_Bits_Mux4 : process (mux3, shift_1, void_bit) is
    begin  -- process Zero_Sixteen_Bits_Mux4
      if (shift_1(0) = '0') then
        -- no additional shifting
        mux4 <= mux3;
      else                              -- '1'
        -- shift another 16 bits
        mux4                             <= (others => void_bit);
        mux4(mux4'left to mux4'right-16) <= mux3(mux3'left+16 to mux3'right);
      end if;
    end process Zero_Sixteen_Bits_Mux4;

    ----------------------------------------
    -- Mux4_Rev
    -- Reverse mux4 for right shift
    ----------------------------------------
    Mux4_Rev : process (mux4) is
      variable rev : shift_type;
    begin  -- process Mux4_Rev
      for I in mux4'left to mux4'right loop
        rev(I) := mux4(mux4'right - I);
      end loop;  -- I
      mux4_reversed <= rev;
    end process Mux4_Rev;

    ----------------------------------------
    -- Barrel_Result_Mux5_PROCESS
    -- Mux to Select final result
    ----------------------------------------
    Barrel_Result_Mux5_PROCESS : process (mux4, mux4_reversed, left_shifting_1) is
    begin  -- process Barrel_Result_Mux5_PROCESS
      if (left_shifting_1) then
        fconv_op_3_shifted <= mux4;
      else
        fconv_op_3_shifted <= mux4_reversed;
      end if;
    end process Barrel_Result_Mux5_PROCESS;

  end block left_right_shifter;

  fconv_op_3 <= fconv_op_3_shifted(0 to 31);

  flt_grs_3(0) <= fconv_op_3_shifted(32);
  flt_grs_3(1) <= fconv_op_3_shifted(33);

  Fix_Sticky_Bit : process (Clk) is
  begin  -- process Fix_Sticky_Bit
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        flt_grs_3(2) <= '0';
      else
        if (not left_shifting) then
          case shift is
            when "00011" => flt_grs_3(2) <= fconv_op_2(31);
            when "00100" => flt_grs_3(2) <= fconv_op_2(30) or fconv_op_2(31);
            when "00101" => flt_grs_3(2) <= fconv_op_2(29) or fconv_op_2(30) or fconv_op_2(31);
            when "00110" => flt_grs_3(2) <= fconv_op_2(28) or fconv_op_2(29) or fconv_op_2(30) or fconv_op_2(31);
            when "00111" => flt_grs_3(2) <= fconv_op_2(27) or fconv_op_2(28) or fconv_op_2(29) or fconv_op_2(30) or fconv_op_2(31);
            when others  => flt_grs_3(2) <= '0';
          end case;
        else
          flt_grs_3(2) <= '0';
        end if;
      end if;
    end if;
  end process Fix_Sticky_Bit;

  op3_control : process (Clk) is
  begin  -- process op3_control
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        fconv_sign_3      <= '0';
        int_op_3          <= false;
        flt_op_3          <= false;
        int_special_res_3 <= (others => '0');
      else
        int_special_res_3 <= int_special_res_2;
        int_op_3          <= int_op_2;
        flt_op_3          <= flt_op_2;
        flt_exp_3         <= std_logic_vector(to_unsigned((158-flt_fsb_2), 8));
        fconv_sign_3      <= fconv_sign_2;
      end if;
    end if;
  end process op3_control;

  Int_Result_ALU : block is
    signal int_res_alu_carry : std_logic_vector(0 to 32);
    signal int_res_alu_sel   : std_logic_vector(0 to 31);
  begin  -- block Int_Result_ALU
    -----------------------------------------------------------------------------
    -- Last adder part for INT operation
    -- 1. Pass the fconv_op_left_3 or fconv_op_right_3
    -- 2. not(fconv_op_left_3 or fconv_op_right_3) + 1
    -----------------------------------------------------------------------------
    int_res_alu_carry(32) <= '1' when (fconv_sign_3 = '1') else '0';

    INT_Result_ALU : for I in 31 downto 0 generate
      
      int_res_alu_sel(I) <= not(fconv_op_3(I)) when fconv_sign_3 = '1' else
                             (fconv_op_3(I));

      int_res_alu_MUXCY_L : MUXCY_L
        port map (
          DI => '0',                     -- [in  std_logic]
          CI => int_res_alu_carry(I+1),  -- [in  std_logic]
          S  => int_res_alu_sel(I),      -- [in  std_logic]
          LO => int_res_alu_carry(I));   -- [out std_logic]

      int_res_alu_XORCY : XORCY
        port map (
          LI => int_res_alu_sel(I),      -- [in  std_logic]
          CI => int_res_alu_carry(I+1),  -- [in  std_logic]
          O  => int_res_alu(I));         -- [out std_logic]

    end generate INT_Result_ALU;
  end block Int_Result_ALU;

  ---------------------------------------------------------------------------
  -- Now we can combine the bits for the final result
  ---------------------------------------------------------------------------
  Fconv_Flt_Res : process (Clk) is
    variable temp_exp : std_logic_vector(0 to 7);
  begin  -- process Fconv_Flt_Res
    if Clk'event and Clk = '1' then     -- rising clock edge
      if (Reset = '1') or (not flt_op_3) then  -- synchronous reset (active high)
        MEM_Flt_Exp_4    <= (others => '0');
        MEM_Flt_Result_4 <= (others => '0');
      else
        MEM_Flt_Exp_4    <= flt_exp_3;
        MEM_Flt_Result_4 <= int_res_alu(8 to 31) & flt_grs_3;
      end if;
    end if;
  end process Fconv_Flt_Res;

  Fconv_Int_Done : process (Clk) is
    variable temp_exp : std_logic_vector(0 to 7);
  begin  -- process Fconv_Int_Done
    if Clk'event and Clk = '1' then     -- rising clock edge
      if (Reset = '1') then             -- synchronous reset (active high)
        MEM_Flt_Done <= false;
        MEM_Int_Done <= false;
        flt_op_4     <= false;
      else
        flt_op_4     <= flt_op_3;
        MEM_Int_Done <= int_op_3;
        MEM_Flt_Done <= flt_op_4;
      end if;
    end if;
  end process Fconv_Int_Done;

  MEM_Int_Done_Early <= int_op_3;
  
  Fconv_Int_Res : process (Clk) is
    variable temp_exp : std_logic_vector(0 to 7);
  begin  -- process Fconv_Int_Res
    if Clk'event and Clk = '1' then     -- rising clock edge
      if (Reset = '1') or (int_special_res_3 /= Normal) or (not int_op_3) then  -- synchronous reset (active high)
        MEM_Int_Result_5(1 to 31) <= (others => '0');
      else
        MEM_Int_Result_5(1 to 31) <= int_res_alu(1 to 31);
      end if;
    end if;
  end process Fconv_Int_Res;

  Fconv_Int_Res_Msb : process (Clk) is
    variable temp_exp : std_logic_vector(0 to 7);
  begin  -- process Fconv_Int_Res_Msb
    if Clk'event and Clk = '1' then     -- rising clock edge
      if (Reset = '1') or (int_special_res_3 = Zero) or (not int_op_3) then
        MEM_Int_Result_5(0) <= '0';
      elsif (int_special_res_3 = Max_Int) then
        MEM_Int_Result_5(0) <= '1';
      else
        MEM_Int_Result_5(0) <= int_res_alu(0);
      end if;
    end if;
  end process Fconv_Int_Res_Msb;
  
end architecture IMP;