exception_registers_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: exception_registers_gti.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- exception_registers_gti.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
--  **                                                                       **
--  **  This text contains proprietary, confidential                         **
--  **  information of Xilinx, Inc. , is distributed by                      **
--  **  under license from Xilinx, Inc., and may be used,                    **
--  **  copied and/or disclosed only pursuant to the terms                   **
--  **  of a valid license agreement with Xilinx, Inc.                       **
--  **                                                                       **
--  **  Unmodified source code is guaranteed to place and route,             **
--  **  function and run at speed according to the datasheet                 **
--  **  specification. Source code is provided "as-is", with no              **
--  **  obligation on the part of Xilinx to provide support.                 **
--  **                                                                       **
--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
--  **                                                                       **
--  **  The Xilinx Support Hotline does not have access to source            **
--  **  code and therefore cannot answer specific questions related          **
--  **  to source HDL. The Xilinx Support Hotline will only be able          **
--  **  to confirm the problem in the Netlist version of the core.           **
--  **                                                                       **
--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        exception_registers_gti.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              exception_registers_gti.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2005-10-04    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types and ISA constants
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

entity exception_registers_gti is
  generic (
    C_FSL_EXCEPTION  : boolean := false;
    C_MAX_FSL_LINKS  : natural;
    C_SAVE_PC_IN_EAR : boolean := false;
    C_USE_MMU        : integer
    );
  port (
    Clk                      : in  std_logic;
    Reset                    : in  std_logic;
    EX_PipeRun               : in  boolean;
    MEM_PipeRun              : in  boolean;
    EX_Instruction_Exception : in  boolean;
    EX_Data_Addr             : in  std_logic_vector(0 to 31);
    EX_PC                    : in  std_logic_vector(0 to 31);
    WB_PC                    : in  std_logic_vector(0 to 31);
    EX_Branch_Target         : in  std_logic_vector(0 to 31);
    EX_Load_BTR              : in  boolean;
    MEM_Sel_SPR_BTR          : in  boolean;  -- Select SPR Branch Target Register
    MEM_Sel_SPR_ESR          : in  boolean;  -- Select SPR exception status register
    MEM_Sel_SPR_EAR          : in  boolean;  -- Select SPR exception address register
    MEM_Sel_SPR_EDR          : in  boolean;  -- Select SPR exception data register
    WB_Clr_ESR               : in  boolean;
    WB_Load_EAR              : in  boolean;
    WB_Load_EDR              : in  boolean;
    WB_Load_ESR              : in  boolean;
    WB_Exception_Kind        : in  EXCEPTION_KIND_TYPE;
    WB_SW_Instr              : in  std_logic;
    WB_Word_Access           : in  std_logic;
    WB_Zone_Protect          : in  std_logic;
    WB_New_ESR_ESS_Rx        : in  GPR_ADDR_TYPE;
    WB_DelaySlot_Instr       : in  boolean;
    WB_Read_Imm_Reg          : in  boolean;
    WB_Read_Imm_Reg_1        : in  boolean;
    WB_FSL_No                : in  natural range 0 to C_MAX_FSL_LINKS-1;  -- Which FSL to operate on
    WB_MEM_Result            : in  DATA_TYPE;
    WB_BTR                   : out BTR_TYPE;
    WB_Excep_Return_Addr     : out std_logic_vector(0 to 31);
    WB_EAR                   : out EAR_TYPE;
    WB_EDR                   : out EDR_TYPE;
    WB_ESR                   : out ESR_TYPE
    );
end entity exception_registers_gti;

architecture IMP of exception_registers_gti is

  constant WORD_BIT       : integer := DATA_TYPE'right - 2;
  constant DWORD_BIT      : integer := DATA_TYPE'right - 3;

  signal reset_ESR : std_logic;

  signal WB_ESR_i : ESR_TYPE;
  signal mem_EAR  : EAR_TYPE;
  signal wb_EAR_i : EAR_TYPE;
  signal wb_EDR_i : EDR_TYPE;
  signal wb_EAR_ii: EAR_TYPE;
  signal mem_BTR  : std_logic_vector(0 to 31);
  
  -- Amount to increment or decrement exception return address by.
  signal incr_decr     : DATA_TYPE;
  signal use_increment : boolean;

begin  -- architecture IMP

  -----------------------------------------------------------------------------
  -- Save the PC or Data address in the EX stage
  -----------------------------------------------------------------------------
  MEM_EAR_DFF: process (Clk) is
  begin  -- process MEM_EAR_DFF
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Reset = '1' then                 -- synchronous reset (active high)
        mem_EAR <= (others => '0');
      elsif (EX_PipeRun) then
        if (C_SAVE_PC_IN_EAR) then
          if (EX_Instruction_Exception) then
            mem_EAR <= EX_PC;
          else
            mem_EAR <= EX_Data_Addr;
          end if;
        else  
          mem_EAR <= EX_Data_Addr;
        end if;
      end if;
    end if;
  end process MEM_EAR_DFF;


  MEM_BTR_DFF: process (Clk) is
  begin  -- process MEM_BTR_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        mem_BTR <= (others => '0');                    
      elsif (EX_Load_BTR) then
        mem_BTR <= EX_Branch_Target;        
      end if;
    end if;
  end process MEM_BTR_DFF;
  
  -----------------------------------------------------------------------------
  -- Save in the MEM stage
  -----------------------------------------------------------------------------
  WB_EAR_DFF: process (Clk) is
  begin  -- process WB_EAR_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then                 -- synchronous reset (active high)
        wb_EAR_i <= (others => '0');
      elsif (MEM_PipeRun) then
        wb_EAR_i <= mem_EAR;
      end if;
    end if;
  end process WB_EAR_DFF;

  WB_BTR_DFF: process (Clk) is
  begin  -- process WB_BTR_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' or not MEM_Sel_SPR_BTR then                 -- synchronous reset (active high)
        WB_BTR   <= (others => '0');
      elsif (MEM_PipeRun) then
        WB_BTR   <= mem_BTR;
      end if;
    end if;
  end process WB_BTR_DFF;

  -----------------------------------------------------------------------------
  -- Save it in the WB stage
  -----------------------------------------------------------------------------
  -- Exception Address Register handling.
  EAR_DFF: process (Clk) is
  begin  -- process EAR_DFF
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Reset = '1' then                 -- synchronous reset (active high)
        WB_EAR_ii <= (others => '0');
      else
        if (wb_Load_EAR) then
          WB_EAR_ii <= wb_EAR_i;
        end if;
      end if;
    end if;
  end process EAR_DFF;

  EAR_Output_DFF: process (Clk) is
  begin  -- process EAR_DFF
    if Clk'event and Clk = '1' then  -- rising clock edge
      if not MEM_Sel_SPR_EAR then                 -- synchronous reset (active high)
        WB_EAR <= (others => '0');
        
      elsif( MEM_PipeRun ) then
        WB_EAR <= wb_EAR_ii;
        
      end if;
    end if;
  end process EAR_Output_DFF;

  -- Exception Data Register handling.
  EDR_DFF: process (Clk) is
  begin  -- process EAR_DFF
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Reset = '1' then                 -- synchronous reset (active high)
        WB_EDR_i <= (others => '0');
      else
        if (wb_Load_EDR) then
          WB_EDR_i <= WB_MEM_Result;
        end if;
      end if;
    end if;
  end process EDR_DFF;

  EDR_Output_DFF: process (Clk) is
  begin  -- process EAR_DFF
    if Clk'event and Clk = '1' then  -- rising clock edge
      if not MEM_Sel_SPR_EDR then                 -- synchronous reset (active high)
        WB_EDR <= (others => '0');
      elsif( MEM_PipeRun ) then
        WB_EDR <= wb_EDR_i;
      end if;
    end if;
  end process EDR_Output_DFF;

  -- Exception Status Register handling.
  reset_ESR <= '1' when WB_Clr_ESR else Reset;
  
  ESR_DFF : process (Clk) is
  begin  -- process ESR_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if reset_ESR = '1' then                     -- synchronous reset (active high)
        WB_ESR_I <= (others => '0');
      else
        if (WB_Load_ESR) then
          if (WB_DelaySlot_Instr) then
            WB_ESR_I(19) <= '1';
          else
            WB_ESR_I(19) <= '0';
          end if;

          -- ESS bits.
          if C_USE_MMU >= C_MMU_PROTECT and
             (WB_Exception_Kind = DATA_STORAGE_EXCEPTION_KIND or
              WB_Exception_Kind = INSTR_STORAGE_EXCEPTION_KIND) then
            WB_ESR_I(20)     <= WB_Zone_Protect;
          else
            WB_ESR_I(20)     <= WB_Word_Access;
          end if;
          WB_ESR_I(21)       <= WB_SW_Instr;
          if( C_FSL_EXCEPTION and ( WB_Exception_Kind = FSL_CTRL_ERR_EXCEPTION_KIND) ) then
            WB_ESR_I(22 to 26) <= std_logic_vector(to_unsigned(WB_FSL_No, 5));
          else
            WB_ESR_I(22 to 26) <= WB_New_ESR_ESS_Rx;
          end if;

          -- EC bits.
          -- Bit 27 of WB_Exception_Kind is currently hardcoded to 0
          -- unless MMU exceptions are used
          if (C_USE_MMU >= C_MMU_PROTECT) then
            WB_ESR_I(EXCEPTION_KIND_TYPE'range) <= WB_Exception_Kind;
          else
            WB_ESR_I(27)       <= '0';
            WB_ESR_I(28 to 31) <= WB_Exception_Kind(28 to 31);
          end if;
        end if;
      end if;
    end if;
  end process ESR_DFF;


  ESR_Output_DFF : process (Clk) is
  begin  -- process ESR_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if not MEM_Sel_SPR_ESR then                     -- synchronous reset (active high)
        WB_ESR <= (others => '0');
      elsif( MEM_PipeRun ) then
        WB_ESR <= WB_ESR_I;
      end if;
    end if;
  end process ESR_Output_DFF;


  ----------------------------------------
  -- Calculate new exception return adress
  ----------------------------------------
  WB_Excep_Return_Addr <=
    std_logic_vector(Unsigned(WB_PC) + unsigned(incr_decr)) when use_increment else
    std_logic_vector(Unsigned(WB_PC) - unsigned(incr_decr));
  
  ----------------------------------------
  -- Increment_PROCESS
  -- Amount to increment or decrement Exception return address by
  -- (FPGA: Creates mask of bits in the PC to increment)
  -- Increments word bit, decrements word bit, or decrements double-word bit
  ----------------------------------------
  Increment_PROCESS: process (WB_Exception_kind, WB_Read_Imm_Reg,
                              WB_DelaySlot_Instr, WB_Read_Imm_Reg_1) is
  begin
    incr_decr <= (others => '0');
    use_increment <= false;

    if (WB_Exception_kind(EXCEPTION_KIND_COMMON_POS) = EXCEPTION_KIND_COMMON_DEC) then
      if (C_USE_MMU < C_MMU_PROTECT) or
         (WB_Exception_kind(EXCEPTION_KIND_TYPE'left) = '0') then
        -- Ordinary exceptions: Return to next instruction
        incr_decr(WORD_BIT) <= '1';
        use_increment       <= true;
      else
        -- MMU exceptions: Redo instruction when returning from exception
        if (WB_Read_Imm_Reg) or (WB_DelaySlot_Instr and not WB_Read_Imm_Reg_1) then
          -- Imm, Instr: Return to Imm
          -- Branch, Instr in delayslot: Return to Branch
          incr_decr(WORD_BIT) <= '1';
        end if;
        if (WB_DelaySlot_Instr and WB_Read_Imm_Reg_1) then
          -- Imm, Branch, Instr in delayslot: Return to Imm
          incr_decr(DWORD_BIT) <= '1'; 
        end if;
      end if;
    end if;
  end process Increment_PROCESS;

end architecture IMP;