microblaze_isa_pkg_body.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: microblaze_isa_pkg_body.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- microblaze_isa_pkg_body.vhd<2>
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        microblaze_isa_pkg_body.vhd<2>
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              microblaze_isa_pkg_body.vhd<2>
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2002-11-12    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

package MicroBlaze_ISA is

  
  
  function Decode_Mnemomics ( Instr : INSTRUCTION_WORD_TYPE) return string is
    variable res_s : string(1 to 15);
    variable len : natural := natural range res_s'range;
  begin  -- Decode_Mnemomics
    -- Decode Major opcode
    case Instr(0 to 5) is
      when Add_Dec     => Result := ADD;
      when RSub_Dec    => Result := RSUB;
      when Addc_Dec    => Result := ADDC;
      when RSubc_Dec   => Result := RSUBC;
      when Addk_Dec    => Result := ADDK;
      when RSubk_Dec   => Result := RSUBK;
      when Addkc_Dec   => Result := ADDKC;
      when RSubkc_Dec  => Result := RSUBKC;
      when Addi_Dec    => Result := ADDI;
      when RSubi_Dec   => Result := RSUBI;
      when Addic_Dec   => Result := ADDIC;
      when RSubic_Dec  => Result := RSUBIC;
      when Addik_Dec   => Result := ADDIK;
      when RSubik_Dec  => Result := RSUBIK;
      when Addikc_Dec  => Result := ADDIKC;
      when RSubikc_Dec => Result := RSUBIKC;

      when MUL_Dec   => Result := MUL;
      when MULI_Dec  => Result := MULI;

      when And_Dec   => Result := \and\;
      when Xor_Dec   => Result := \xor\;
      when OR_Dec    => Result := \or\;
      when ANDN_Dec  => Result := ANDN;
      when Andi_Dec  => Result := ANDI;
      when Xori_Dec  => Result := XORI;
      when ORI_Dec   => Result := ORI;
      when ANDNI_Dec => Result := ANDNI;

      when SRx_Dec =>
        case Instr(SRX_POS_TYPE) is
          when SRA_Dec => Result := \sra\;
          when SRC_Dec => Result := SRC;
          when SRL_Dec => Result := \srl\;
          when SEXT_DEC =>
            if (Instr(SEXTX_POS) = SEXT8_DEC) then
              Result := SEXT8;
            else
              Result := SEXT16;
            end if;
          when others  => Result := Illegal;
        end case;

        
      when Imm_Dec => Result := IMM;

      when MxS_Dec =>
        if Instr(MXS_POS) = MTS_DEC then
          Result := MTS;
        else
          Result := MFS;
        end if;
        
      when BRxx_Dec =>
        brx_LDA := Instr(BRXX_LINK_POS) & Instr(BRXX_DELAY_POS) & Instr(BRXX_ABS_POS);
        case brx_LDA is
          when "000"  => Result := BR;
          when "001"  => Result := BRA;
          when "010"  => Result := BRD;
          when "011"  => Result := BRAD;
          when "100"  => Result := BRL;
          when "101"  => Result := BRAL;
          when "110"  => Result := BRLD;
          when "111"  => Result := BRALD;
          when others => null;
        end case;
        
      when BRxxI_Dec =>
        brx_LDA := Instr(BRXX_LINK_POS) & Instr(BRXX_DELAY_POS) & Instr(BRXX_ABS_POS);
        case brx_LDA is
          when "000"  => Result := BRI;
          when "001"  => Result := BRAI;
          when "010"  => Result := BRDI;
          when "011"  => Result := BRADI;
          when "100"  => Result := BRLI;
          when "101"  => Result := BRALI;
          when "110"  => Result := BRLDI;
          when "111"  => Result := BRALDI;
          when others => null;
        end case;

      when Bxx_Dec =>
        if (Instr(BXX_DELAY_POS) = '1') then
          case Instr(BXX_POS_TYPE) is
            when BEQ_Dec => Result := BEQD;
            when BNE_Dec => Result := BNED;
            when BLT_Dec => Result := BLTD;
            when BLE_Dec => Result := BLED;
            when BGT_Dec => Result := BGTD;
            when BGE_Dec => Result := BGED;
            when others  => null;
          end case;
        else
          case Instr(BXX_POS_TYPE) is
            when BEQ_Dec => Result := BEQ;
            when BNE_Dec => Result := BNE;
            when BLT_Dec => Result := BLT;
            when BLE_Dec => Result := BLE;
            when BGT_Dec => Result := BGT;
            when BGE_Dec => Result := BGE;
            when others  => null;
          end case;
        end if;

      when BxxI_Dec =>
        if (Instr(BXX_DELAY_POS) = '1') then
          case Instr(BXX_POS_TYPE) is
            when BEQ_Dec => Result := BEQID;
            when BNE_Dec => Result := BNEID;
            when BLT_Dec => Result := BLTID;
            when BLE_Dec => Result := BLEID;
            when BGT_Dec => Result := BGTID;
            when BGE_Dec => Result := BGEID;
            when others  => null;
          end case;
        else
          case Instr(BXX_POS_TYPE) is
            when BEQ_Dec => Result := BEQI;
            when BNE_Dec => Result := BNEI;
            when BLT_Dec => Result := BLTI;
            when BLE_Dec => Result := BLEI;
            when BGT_Dec => Result := BGTI;
            when BGE_Dec => Result := BGEI;
            when others  => null;
          end case;
        end if;

      when RTx_Dec =>
        if Instr(21) = '0' then
          Result := RTSD;
        else
          Result := RTID;
        end if;

      when LBU_Dec  => Result := LBU;
      when SB_Dec   => Result := SB;
      when LHU_Dec  => Result := LHU;
      when SH_Dec   => Result := SH;
      when LW_Dec   => Result := LW;
      when SW_Dec   => Result := SW;
      when LBUI_Dec => Result := LBUI;
      when SBI_Dec  => Result := SBI;
      when LHUI_Dec => Result := LHUI;
      when SHI_Dec  => Result := SHI;
      when LWI_Dec  => Result := LWI;
      when SWI_Dec  => Result := SWI;
      when others   => null;
    end case;

    return Result;
    
  end Decode_Mnemomics;

end package body MicroBlaze_ISA;