comparator.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: comparator.vhd,v 1.3 2007/11/09 13:06:27 stefana Exp $
-------------------------------------------------------------------------------
-- comparator_gti.vhd - Entity and architecture
--
--  ***************************************************************************
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--  **  standard level Xilinx Hotline support, and will only address         **
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--
-------------------------------------------------------------------------------
-- Filename:        comparator_gti.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              comparator_gti.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.3 $
-- Date:            $Date: 2007/11/09 13:06:27 $
--
-- History:
--   goran  2006-04-11    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

library unisim;
use unisim.vcomponents.all;

entity comparator is
  generic (
    C_TARGET    : TARGET_FAMILY_TYPE;
    C_IS_FIRST  : boolean;
    C_SIZE      : natural);
  port (
    Carry_IN  : in  std_logic;
    DI        : in  std_logic;
    A         : in  std_logic_vector(0 to C_SIZE-1);
    B         : in  std_logic_vector(0 to C_SIZE-1);
    Carry_OUT : out std_logic);
end entity comparator;

architecture IMP of comparator is
begin  -- architecture IMP

  -----------------------------------------------------------------------------
  -- FPGA implementation
  -----------------------------------------------------------------------------
  Using_FPGA : if (C_TARGET /= RTL) generate
    constant carry_chain_length : natural := (C_SIZE + 1)/2;
    signal carry_sel   : std_logic_vector(0 to carry_chain_length-1);
    signal carry_chain : std_logic_vector(0 to carry_chain_length);
    signal A_i : std_logic_vector(0 to carry_chain_length*2 - 1);
    signal B_i : std_logic_vector(0 to carry_chain_length*2 - 1);
  begin
    
    input_size_padding : process (A, B) is
    begin  -- process input_size_padding
      A_i                <= (others => '0');
      A_i(0 to C_SIZE-1) <= A;
      B_i                <= (others => '0');
      B_i(0 to C_SIZE-1) <= B;
    end process input_size_padding;

    carry_chain(0) <= Carry_IN;

    Comp_Carry_Chain : for I in 0 to carry_chain_length-1 generate
      carry_sel(I) <= '1' when A_i(I*2 to I*2+1) = B_i(I*2 to I*2+1) else '0';
      MUXCY_I : MUXCY_L
        port map (
          DI => DI,
          CI => carry_chain(I),
          S  => carry_sel(I),
          LO => carry_chain(I+1));    
    end generate Comp_Carry_Chain;

    Carry_OUT <= carry_chain(carry_chain_length);

  end generate Using_FPGA;

  -----------------------------------------------------------------------------
  -- RTL Implementation
  -----------------------------------------------------------------------------
  Using_RTL: if (C_TARGET = RTL) generate
    Carry_OUT <= Carry_IN when A = B else DI;
  end generate Using_RTL;
end architecture IMP;