decode.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

      Buffer_Full : out boolean;
      Instr_OF    : out std_logic_vector(0 to 31+C_IEXT_BUS_EXCEPTION+C_FSL_ATOMIC);
      Buffer_Addr : out std_logic_vector(0 to 3));
  end component PreFetch_Buffer;


  -----------------------------------------------------------------------------
  -- Pipecontrol signals
  -----------------------------------------------------------------------------
  constant C_FSL_ATOMIC   : integer := C_USE_EXTENDED_FSL_INSTR;
  
  constant FSL_EXCEPTION_ON  : boolean := ( C_FSL_LINKS > 0 ) and (C_FSL_EXCEPTION /= 0) and (C_USE_EXTENDED_FSL_INSTR /= 0);
  
  constant C_EXCEPTIONS : boolean := (C_UNALIGNED_EXCEPTIONS /= 0) or
                                     (C_ILL_OPCODE_EXCEPTION /= 0) or
                                     (C_DIV_ZERO_EXCEPTION   /= 0) or
                                     (C_FPU_EXCEPTION        /= 0) or
                                     (FSL_EXCEPTION_ON           ) or
                                     (C_DOPB_BUS_EXCEPTION   /= 0) or
                                     (C_IOPB_BUS_EXCEPTION   /= 0) or
                                     (C_DPLB_BUS_EXCEPTION   /= 0) or
                                     (C_IPLB_BUS_EXCEPTION   /= 0);

  constant C_IEXT_BUS_EXCEPTION : integer := C_IOPB_BUS_EXCEPTION +
                                             C_IPLB_BUS_EXCEPTION -
                                             -- Added to make sure that the
                                             -- result is always 0 or 1 even if
                                             -- both parameters are set
                                             (C_IOPB_BUS_EXCEPTION*C_IPLB_BUS_EXCEPTION);
                                             
  constant C_PREFETCH_ATOMIC_FSL_POS  : integer:= 32 + C_IEXT_BUS_EXCEPTION + C_FSL_ATOMIC - 1;
  
  signal   clean_iReady  : std_logic;
  signal   buffer_Full   : boolean;
  signal   buffer_Full_I : std_logic;
  signal   instr_OF      : std_logic_vector(0 to 31+C_IEXT_BUS_EXCEPTION+C_FSL_ATOMIC);

  signal reset_n : std_logic;

  signal iFetch_I      : rboolean;
  signal ifetch_carry1 : std_logic;
  signal ifetch_carry2 : std_logic;
  signal ifetch_carry3 : std_logic;

  signal i_AS_I                    : rboolean;
  signal of_PipeRun_s_I            : std_logic;
  signal of_PipeRun_I              : rboolean;
  signal of_PipeRun_Select         : std_logic;
  signal of_PipeRun_without_dready : std_logic;
  signal of_Valid                  : boolean;
  signal of_Valid_S                : std_logic;
  signal ex_Valid                  : boolean;
  signal ex_Valid_1st_cycle        : boolean;
  signal ex_Valid_I                : std_logic;
  signal load_Store_i              : boolean;
  signal load_Store                : boolean;
  signal load_Store_without_dbg    : std_logic;
  signal iFetch_In_Progress        : boolean;
  signal iFetch_In_Progress_n      : std_logic;

  signal mul_Executing         : boolean;
  signal mul_Executing_delayed : std_logic;
  signal mul_Executing_done    : std_logic;
  signal mul_Executing_S       : std_logic;

  signal stall_pipe_i : std_logic;
  signal stall_pipe : std_logic;
  
  attribute keep                     : string;
  attribute keep of of_PipeRun_s_I   : signal is "true";

  signal d_AS_I : std_logic;

  -----------------------------------------------------------------------------
  -- External Signals used internally
  -----------------------------------------------------------------------------
  signal write_Addr_I             : std_logic_vector(Write_Addr'range);
  signal write_Reg                : boolean;
  signal write_Reg_I              : boolean;
  signal write_Reg_S              : std_logic;
  signal writing                  : boolean;
  signal write_MSR_I              : rboolean;
  signal write_FSR_I              : boolean;
  signal write_FSR_II             : boolean;
  signal other_Write              : boolean;
  signal write_Valid_Reg          : boolean;
  signal dready_Valid             : boolean;
  signal write_mem_valid_in_ex    : boolean;
  signal write_other_valid_in_ex  : boolean;
  signal dready_Valid_S           : std_logic;
  signal other_Write_S            : std_logic;
  signal write_Valid_Reg_S        : std_logic;
  signal write_Reg_I_S            : std_logic;

  signal mtsmsr_write_i  : boolean;
  signal mtsmsr_write_ii : boolean;

  signal MSRxxx_Instr_i : rboolean;

  -----------------------------------------------------------------------------
  -- Signals for operand decode and interrupts
  -----------------------------------------------------------------------------
  signal using_Imm             : boolean;
  signal opsel1_SPR_Select_1   : std_logic;
  signal opsel1_SPR_Select_2_1 : std_logic;
  signal opsel1_SPR_Select_2_2 : std_logic;
  signal opsel1_SPR_Select     : std_logic;
  signal opsel1_SPR_Select_II  : std_logic;
  signal opsel1_SPR_I          : std_logic;
  signal opsel1_SPR_II         : std_logic;
  signal enable_Interrupts_I   : rboolean;
  signal set_BIP_I             : rboolean;
  signal reset_BIP_I           : rboolean;

  -----------------------------------------------------------------------------
  -- Signals for Carry handling
  -----------------------------------------------------------------------------
  signal write_Carry_I        : boolean;
  signal write_Carry_I_S      : std_logic;
  signal new_Carry_I          : std_logic;
  signal use_ALU_Carry        : rboolean;
  signal select_ALU_Carry     : boolean;
  signal select_ALU_Carry_S   : std_logic;
  signal correct_Carry        : std_logic;
  signal MSR_Carry            : std_logic;
  signal correct_Carry_I      : std_logic;
  signal correct_Carry_II     : std_logic;
  signal correct_Carry_Select : std_logic;
  signal Carry_Select         : std_logic;
  signal sub_Carry            : std_logic;

  signal msrxxx_carry         : std_logic;
  signal msrxxx_write_carry   : std_logic;
  
  -----------------------------------------------------------------------------
  -- Signal for ALU decoding
  -----------------------------------------------------------------------------
  signal alu_Op_I             : std_logic_vector(0 to 1);
  signal alu_Op_II            : std_logic_vector(0 to 1);
  signal alu_Op_DFF           : std_logic_vector(0 to 1);

  -----------------------------------------------------------------------------
  -- Signal for handling jumps
  -----------------------------------------------------------------------------

  signal intr_or_delay_slot_jump : std_logic;
  signal only_intr               : std_logic;
  signal delay_slot_jump         : std_logic;
  signal EX_delayslot_Instr_I    : boolean;

  signal force2_i           : std_logic;
  signal force1_i           : std_logic;
  signal force_Val2_n_i     : std_logic;
  signal force_Val1_i       : std_logic;
  signal use_Reg_Neg_S_i    : std_logic;
  signal use_Reg_Neg_DI_i   : std_logic;
  signal Reg_Test_Equal_i   : std_logic;
  signal Reg_Test_Equal_N_i : std_logic;

  signal force2         : std_logic;
  signal force1         : std_logic;
  signal force_Val2_N   : std_logic;
  signal force_Val1     : std_logic;
  signal use_Reg_Neg_S  : std_logic;
  signal use_Reg_Neg_DI : std_logic;
  signal force_jump2    : std_logic;
  signal force_DI2      : std_logic;
  signal force_jump1    : std_logic;
  signal force_DI1      : std_logic;

  signal jump_carry3_sel : std_logic;  -- Fix for handling delay_slots and slow memory 2004-05-11
  signal jump_Carry1     : std_logic;
  signal jump_Carry2     : std_logic;
  signal jump_Carry3     : std_logic;
  signal jump_I          : rboolean;
  signal jump2_I         : boolean;
  signal inHibit_EX      : boolean;
  signal inHibit_EX_Rst  : boolean;

  signal missed_IFetch     : boolean;
  signal nonvalid_IFetch_n : std_logic;
  signal if_valid          : boolean;   -- Added for getting the same signal as
                                        -- 5 stage pipeline. Needed for ISA tests

  signal jump2_I_1           : boolean;
  signal Blocked_Valid_Instr : std_logic;

  -----------------------------------------------------------------------------
  -- Signals for Interrupt/Exception handling
  -----------------------------------------------------------------------------
  signal take_Intr_Now_Select : std_logic;
  signal take_Intr_Now_Select_I : std_logic;
  signal take_Intr_Now_I      : std_logic;
  signal take_Intr_Now_II     : std_logic;
  signal take_Intr_Now_III    : std_logic;
  signal take_Intr_Now_s      : std_logic;
  signal take_Intr_Now        : rboolean;
  signal take_Intr_Now_Early  : rboolean;
  signal take_intr_2nd_cycle      : boolean;
  signal take_Break_2nd_cycle     : boolean;
  signal take_NM_Break_2nd_cycle  : boolean;
  signal take_Intr_2nd_Phase  : rboolean;
  signal take_intr_Done       : boolean;
  signal break_Pipe_i         : boolean;
  signal break_Pipe           : boolean;
  signal take_Break           : boolean;
  signal take_Exc             : rboolean;
  signal Take_Exc_2nd_cycle   : boolean;
  signal take_intr            : boolean;
  signal take_NM_Break        : boolean;
  signal ext_nm_brk_i         : std_logic;
  signal clr_NM_BRK           : std_logic;
  

  -----------------------------------------------------------------------------
  -- signals for Debug Logic doing Memory accesses
  -----------------------------------------------------------------------------
  signal doublet_Read_i : boolean;
  signal quadlet_Read_i : boolean;
  signal byte_i         : boolean;
  signal doublet_i      : boolean;
  signal quadlet_i      : boolean;

  -----------------------------------------------------------------------------
  -- Signals for FSL Links
  -----------------------------------------------------------------------------
  signal if_fsl_atomic          : std_logic;
  signal of_fsl_put             : std_logic;
  signal of_fsl_get             : std_logic;
  signal of_fsl_test            : std_logic;
  signal of_fsl_control         : std_logic;
  signal of_fsl_blocking        : std_logic;
  signal of_fsl_exceptionable   : std_logic;
  signal of_fsl_atomic          : std_logic;
  signal FSL_Get_I              : std_logic;
  signal FSL_Put_I              : std_logic;
  signal EX_MSR_Load_FSL_C_I    : std_logic;
  signal FSL_Will_Break         : std_logic;
  signal FSL_Will_Break_No_Dbg  : std_logic;
  signal FSL_Break              : std_logic;
  signal FSL_Interrupted        : std_logic;
  signal FSL_Exception_I        : std_logic;
  signal FSL_Exceptionable      : std_logic;
  signal FSL_Atomic             : std_logic;
  signal Write_FSL_Result       : rboolean;

  -----------------------------------------------------------------------------
  -- Signals for divide
  -----------------------------------------------------------------------------
  signal Start_Div_i : std_logic;
  signal div_started : std_logic := '0';
  signal Write_DIV_result : boolean;  

  -----------------------------------------------------------------------------
  -- Signals for FPU
  -----------------------------------------------------------------------------
  signal Start_FPU_i : std_logic;
  signal fpu_started : std_logic := '0';
  signal Write_FPU_result : boolean;  
  
  signal Write_ICache_I : boolean;
  signal Write_DCache_I : boolean;

  -----------------------------------------------------------------------------
  -- Signals for decode logic
  -----------------------------------------------------------------------------

  signal Load_Store_Instr_Addr_i      : std_logic;
  signal Load_Store_Instr_Addr_Stored : std_logic;

  signal Instr_I : std_logic_vector(0 to 31+C_IEXT_BUS_EXCEPTION);
  signal Instr_II: std_logic_vector(0 to 31+C_IEXT_BUS_EXCEPTION+C_FSL_ATOMIC);

  constant C_USE_ICACHE_WR : boolean := (C_ALLOW_ICACHE_WR > 0) and (C_USE_ICACHE > 0);
  constant C_USE_DCACHE_WR : boolean := (C_ALLOW_DCACHE_WR > 0) and (C_USE_DCACHE > 0);

  -------------------------------------------------------------------------------
  -- Exception
  -------------------------------------------------------------------------------

  signal FPU_Exception_i   : std_logic;
  signal Div_Exception     : std_logic;
  signal DExt_Exception    : std_logic;
  signal IExt_Exception    : rboolean;
  signal IExt_Exception_EX : std_logic;
  signal Illegal_Opcode    : rboolean;
  signal Illegal_Opcode_I  : std_logic;
  signal Illegal_Opcode_EX : std_logic;


  signal stop_mem_access : std_logic;
  signal unalignment     : std_logic;
  signal unalignment_exc : std_logic;
  signal unalignment_1   : std_logic;

  signal Exc_Blocking : std_logic;

  signal exception : std_logic;

  signal Prefetch_Reset : boolean;

  signal write_load_result : boolean;
  
  signal ex_not_mul_op_i   : rboolean;
  signal ex_mulh_instr_i   : rboolean;
  signal ex_mulhu_instr_i  : rboolean;
  signal ex_mulhsu_instr_i : rboolean;

  signal mem_sel_spr_pvr_i : rboolean;

  -- trace signals
  signal trace_valid_instr_part1 : std_logic;

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------

begin  -- IMP

  -----------------------------------------------------------------------------
  -- Common code between FPGA and RTL
  -----------------------------------------------------------------------------
  Using_FPU_Exception: if (C_FPU_EXCEPTION /= 0) generate
    FPU_Exception_i <= FPU_Excep;
  end generate Using_FPU_Exception;

  No_FPU_Exception: if (C_FPU_EXCEPTION = 0) generate
    FPU_Exception_i <= '0';
  end generate No_FPU_Exception;

  FPU_Exception    <= FPU_Exception_i;
  
  Detect_Div_By_Zero : if (C_DIV_ZERO_EXCEPTION /= 0) generate
    Div_Exception <= Div_By_Zero;
  end generate Detect_Div_By_Zero;