pc_module.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: pc_module.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- PC_Module - entity/architecture
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        pc_module.vhd
-- Version:         v1.00a
-- Description:     Implements the Program Counter (PC)
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              pc_module.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity PC_Module is
  generic (
    -- Size generics
    C_DATA_SIZE     : natural range 4 to 64 := 32;
    C_TARGET        : TARGET_FAMILY_TYPE;
    C_PC_START_ADDR : string                := "00000000"
    );
  port (
    Clk   : in std_logic;
    Reset : in boolean;

    Stop_Instr_Fetch : in std_logic;
    OF_PipeRun       : in boolean;

    PC_Incr    : in boolean;
    Jump       : in boolean;
    ALU_Result : in std_logic_vector(0 to C_DATA_SIZE-1);

    PC_Write    : in boolean;
    IReady      : in std_logic;
    Buffer_Addr : in std_logic_vector(0 to 3);

    PC_OF      : out std_logic_vector(0 to C_DATA_SIZE-1);
    PC_EX      : out std_logic_vector(0 to C_DATA_SIZE-1);
    Instr_Addr : out std_logic_vector(0 to C_DATA_SIZE-1)
    );

end entity PC_Module;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of PC_Module is

  component PC_Bit is
    generic (
      C_TARGET      : TARGET_FAMILY_TYPE;
      C_RESET_VALUE : std_logic);
    port (
      Clk          : in  std_logic;
      Reset        : in  boolean;
      OF_PipeRun   : in  boolean;
      Increment    : in  std_logic;
      Carry_In     : in  std_logic;
      Carry_Out    : out std_logic;
      Jump         : in  boolean;
      ALU_Result   : in  std_logic;
      PC_Write     : in  boolean;
      IReady       : in  std_logic;
      Buffer_Addr  : in  std_logic_vector(0 to 3);
      PC_OF        : out std_logic;
      PC_EX        : out std_logic;
      Instr_Addr   : out std_logic);
  end component PC_Bit;

  constant PC_RESET_VALUE : std_logic_vector(0 to C_DATA_SIZE-1) :=
    std_logic_vector(to_signed(String_To_Int(C_PC_START_ADDR)-4, C_DATA_SIZE));

  -- Signal to indicate if each bit in the PC is incremented
  signal increment : std_logic_vector(0 to C_DATA_SIZE-1);

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------

begin

  -- Increment PC by indicating increment of word bit
  Fix_Increment_Bus : process (PC_Incr) is
  begin  -- process Fix_Increment_Bus\
    increment <= (others => '0');
    if (PC_Incr) then
      increment(C_DATA_SIZE-3) <= '1';
    else
      increment(C_DATA_SIZE-3) <= '0';
    end if;
  end process Fix_Increment_Bus;

  Using_FPGA : if (C_TARGET /= RTL) generate

    signal normal_piperun : boolean;

    -- Update PC
    signal pc_write_I : boolean;

    -- Carry from previous PC bit
    signal Carry : std_logic_vector(0 to C_DATA_SIZE);
  
    attribute MAX_FANOUT                    : string;
    attribute uselowskewlines               : string;
    attribute uselowskewlines of pc_write_I : signal is "yes";
    attribute MAX_FANOUT of pc_write_I      : signal is "1000";
    attribute MAX_FANOUT of normal_piperun  : signal is "1000";
  begin

    normal_piperun <= OF_PipeRun and (Stop_Instr_Fetch = '0');

    -- Update PC
    pc_Write_I <= PC_Write;

    -----------------------------------------------------------------------------
    -- Handles PC Incrementer and Jump multiplexor
    -----------------------------------------------------------------------------
    Carry(C_DATA_SIZE) <= '0';

    PC_GEN : for I in C_DATA_SIZE-1 downto 0 generate
      PC_Bit_I : PC_Bit
        generic map (
          C_TARGET      => C_TARGET,
          C_RESET_VALUE => PC_RESET_VALUE(I)
          )
        port map (
          Clk         => Clk,             -- [in]
          Reset       => Reset,           -- [in]
          OF_PipeRun  => normal_piperun,  -- [in]
          Increment   => increment(I),    -- [in]
          Carry_In    => Carry(I+1),      -- [in]
          Carry_Out   => Carry(I),        -- [out]
          Jump        => Jump,            -- [in]
          ALU_Result  => ALU_Result(I),   -- [in]
          PC_Write    => pc_Write_I,      -- [in]
          IReady      => IReady,          -- [in]
          Buffer_Addr => Buffer_Addr,     -- [in]
          PC_OF       => PC_OF(I),        -- [out]
          PC_EX       => PC_EX(I),        -- [out]
          Instr_Addr  => Instr_Addr(I));  -- [out]

    end generate PC_GEN;
  end generate Using_FPGA;

  Using_RTL : if (C_TARGET = RTL) generate
    signal normal_piperun : boolean;

    signal new_PC    : std_logic_vector(0 to C_DATA_SIZE-1);
    signal pc_I      : std_logic_vector(0 to C_DATA_SIZE-1) := (others => '0');
    signal pc_OF_I   : std_logic_vector(0 to C_DATA_SIZE-1);
    type   SRL16_BUFFER_TYPE is array(0 to 15) of std_logic_vector(0 to C_DATA_SIZE-1);
    signal PC_Buffer : SRL16_BUFFER_TYPE := (others => (others => '0'));

    signal PC_EX_i      : std_logic_vector(0 to C_DATA_SIZE-1) := (others => '0');
  begin

    normal_piperun <= OF_PipeRun and (Stop_Instr_Fetch = '0');

    New_PC_Calc: process (ALU_Result, Jump, pc_I, Increment) is
    begin  -- process New_PC_Calc
      if (Jump) then
        new_PC <= ALU_Result;
      else
        new_PC <= std_logic_vector(unsigned(pc_I) + unsigned(increment));
      end if;
    end process New_PC_Calc;

    Instr_Addr <= new_PC;

    PC_OF_DFF : process (Clk) is
    begin  -- process PC_OF_DFF
      if Clk'event and Clk = '1' then  -- rising clock edge
        if Reset then
          pc_I <= PC_RESET_VALUE;
        else
          if (PC_Write) then
            pc_I <= new_PC;
          end if;
        end if;
      end if;
    end process PC_OF_DFF;

    pc_OF_I <= PC_Buffer(to_integer(unsigned(Buffer_Addr)));
    PC_OF   <= pc_OF_I;

    PC_Buffer_Handle : process (Clk) is
    begin  -- process PC_Buffer_Handle
      if Clk'event and Clk = '1' then   -- rising clock edge
        if (IReady = '1') then
          PC_Buffer(0) <= pc_I;
          for I in 1 to 15 loop
            PC_Buffer(I) <= PC_Buffer(I-1);
          end loop;  -- I
        end if;
      end if;
    end process PC_Buffer_Handle;

    PC_EX_DFF : process (Clk) is
    begin  -- process PC_EX_DFF
      if Clk'event and Clk = '1' then   -- rising clock edge
        if (normal_piperun) then
          PC_EX_i <= pc_OF_I;
        end if;
      end if;
    end process PC_EX_DFF;

    PC_EX <= PC_EX_i;
    
  end generate Using_RTL;

end architecture IMP;