pc_bit.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: pc_bit.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- PC_Bit - entity/architecture 
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        pc_bit.vhd
-- Version:         v1.00a
-- Description:     Implements 1 bit of the PC
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              pc_bit.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;


library Unisim;
use Unisim.vcomponents.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity PC_Bit is
  generic (
    -- Size generics
    C_TARGET      : TARGET_FAMILY_TYPE;
    C_RESET_VALUE : std_logic          := '1'
    );
  port (
    Clk   : in std_logic;
    Reset : in boolean;

    OF_PipeRun : in boolean;

    Increment : in  std_logic;
    Carry_In  : in  std_logic;
    Carry_Out : out std_logic;

    Jump        : in boolean;
    ALU_Result  : in std_logic;
    PC_Write    : in boolean;
    IReady      : in std_logic;
    Buffer_Addr : in std_logic_vector(0 to 3);

    PC_OF : out std_logic;
    PC_EX : out std_logic;

    Instr_Addr : out std_logic
    );

end entity PC_Bit;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of PC_Bit is
  signal jump_I         : std_logic;
  signal pc_Write_I     : std_logic;
  signal rst            : std_logic;
  signal run_Pipe       : std_logic;

  signal new_PC  : std_logic;
  signal pc_I    : std_logic;
  signal pc_OF_I : std_logic;

  signal xor_Sum : std_logic;
  signal pc_Sum  : std_logic;

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
  
begin

  jump_I     <= '1' when Jump       else '0';
  pc_Write_I <= '1' when PC_Write   else '0';
  rst        <= '1' when Reset      else '0';
  run_Pipe   <= '1' when OF_PipeRun else '0';

  -----------------------------------------------------------------------------
  -- Handles PC Incrementer and Jump multiplexor
  -----------------------------------------------------------------------------

  -- XOR_SUM <= PC_I xor Increment; => Init = 0110 (0006)
  -- XOR_Sum <= PC_I xor Increment when Dbg_PC_Write = '0' else Dbg_PC

  SUM_I : LUT4
    generic map(
      INIT => X"F066"
      )
    port map (
      O  => xor_SUM,                    -- [out]
      I0 => Increment,                  -- [in]
      I1 => pc_i,                       -- [in]
      I2 => '0',                     -- [in]
      I3 => '0');            -- [in]

  MUXCY_X : MUXCY_L
    port map (
      DI => Increment,
      CI => Carry_In,
      S  => xor_Sum,
      LO => Carry_Out);

  XOR_X : XORCY
    port map (
      LI => xor_Sum,
      CI => Carry_In,
      O  => pc_Sum);

  NewPC_Mux : LUT4
    generic map(
      INIT => X"AACA"
      )
    port map (
      O  => new_PC,                     -- [out]
      I0 => pc_Sum,                     -- [in]
      I1 => ALU_Result,                 -- [in]
      I2 => jump_I,                     -- [in]
      I3 => '0');            -- [in]

  -----------------------------------------------------------------------------
  -- Handles the PCs
  -----------------------------------------------------------------------------
  Set_DFF : if C_RESET_VALUE = '1' generate
    PC_IF_DFF : FDSE
      port map (
        Q   => pc_I,                    -- [out]
        D   => new_PC,                  -- [in]
        C   => Clk,                     -- [in]
        CE  => pc_Write_I,              -- [in]
        S   => rst);                    -- [in]
  end generate Set_DFF;

  Reset_DFF : if C_RESET_VALUE = '0' generate
    PC_IF_DFF : FDRE
      port map (
        Q   => pc_I,                    -- [out]
        D   => new_PC,                  -- [in]
        C   => Clk,                     -- [in]
        CE  => pc_Write_I,              -- [in]
        R   => rst);                    -- [in]
  end generate Reset_DFF;

  PC_OF_Buffer : SRL16E
    port map (
      CE  => IReady,                    -- [in]
      D   => PC_I,                      -- [in]
      Clk => Clk,                       -- [in]
      A0  => Buffer_Addr(3),            -- [in]
      A1  => Buffer_Addr(2),            -- [in]
      A2  => Buffer_Addr(1),            -- [in]
      A3  => Buffer_Addr(0),            -- [in]
      Q   => pc_OF_I);                  -- [out]

--   SRL16_Shift: process (Reset,Clk) is
--   begin  -- process SRL16_Shift
--     if (Reset) then
--       SRL16_Data <= (others => '0');
--     elsif Clk'event and Clk = '1' then     -- rising clock edge
--       if (IReady = '1') then
--         SRL16_Data <= PC_I & SRL16_Data(0 to 14);
--       end if;
--     end if;
--   end process SRL16_Shift;

--   pc_OF_I <= SRL16_Data(to_integer(unsigned(Buffer_Addr)));
  
  PC_OF      <= pc_OF_I;
  Instr_Addr <= new_PC;


  PC_EX_DFF : FDE
    port map (
      Q  => PC_EX,
      D  => pc_OF_I,
      CE => run_Pipe,
      C  => Clk
      );

end architecture IMP;