find_first_bit.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: find_first_bit.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- find_first_bit.vhd - Entity and architecture
--
--  ***************************************************************************
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--  **  standard level Xilinx Hotline support, and will only address         **
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--
-------------------------------------------------------------------------------
-- Filename:        find_first_bit.vhd
--
-- Description:     Find the first bit that is 1
--                  
-- VHDL-Standard:   VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:   
--              find_first_bit.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2006-08-09    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types and ISA constants
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

entity find_first_bit is 
  port (
    -- Vector to check for first set bit
    MEM_Mant           : in  std_logic_vector(FPU_MANT_TYPE'left-1 to FPU_MANT_TYPE'right+1);

    -- Position 0-24 of first set bit
    MEM_Mant_One_Pos   : out std_logic_vector(FPU_MANT_BIT_POS);
    -- All bits are zero
    MEM_Mant_One_Found : out std_logic);
end entity find_first_bit;

architecture IMP of find_first_bit is
  signal in_vec : std_logic_vector(0 to FPU_MANT_TYPE'length+1);

  -- First level signals
  signal sel1_0 : std_logic_vector(0 to 2);
  signal sel1_1 : std_logic_vector(0 to 2);
  signal sel1   : std_logic_vector(0 to 2);
  type two_bits_array is array (natural range 0 to 2) of std_logic_vector(0 to 1);
  signal res1_0 : two_bits_array;
  signal res1_1 : two_bits_array;
  type three_bits_array is array (natural range 0 to 2) of std_logic_vector(0 to 2);
  signal res1 : three_bits_array;

  -- Second level signals
  signal res2_1 : std_logic_vector(0 to 3);
  signal sel2_1 : std_logic;
  signal res2_2 : std_logic_vector(0 to 3);
  signal sel2_2 : std_logic;
  
begin  -- architecture IMP
  in_vec <= MEM_Mant;

  -----------------------------------------------------------------------------
  -- 1) Pos(2 to 4): Check bits 0-7, 8-15, 16-23
  --    Set selector bit if any of the bits in one of the sets is 1
  -- 2) Pos(1): based on the selector bits and In_Vec(24)
  -- 3) Pos(0): selector bit 16-24 (and not selector 0-15)
  --
  -- Pos(0 to 4) = "00000" and Found = '0' if no bits are set
  -----------------------------------------------------------------------------

  -----------------------------------------------------------------------------
  -- 1) Check bits 0-7, 8-15, and 16-23
  -- Check 3 sets of 8 bits
  -----------------------------------------------------------------------------
  First_Level: for I in 0 to 2 generate
    ---------------------------------------------------------------------------
    -- This checks 8 bits at a time
    --
    -- 0123 4567 | sel1_0 sel1_1 res1_0 res1_1 res1 sel1
    --           |                0 1    0 1   012
    -- ---- ---- |   -      -     - -    - -   ---   -
    -- 1xxx xxxx |   1      0     0 0    x x   000   1
    -- 01xx xxxx |   1      0     0 1    x x   001   1
    -- 001x xxxx |   1      0     1 0    x x   010   1
    -- 0001 xxxx |   1      0     1 1    x x   011   1
    -- 0000 1xxx |   0      1     0 0    0 0   100   1
    -- 0000 01xx |   0      1     0 0    0 1   101   1
    -- 0000 001x |   0      1     0 0    1 0   110   1
    -- 0000 0001 |   0      1     0 0    1 1   111   1
    -- 0000 0000 |   0      0     0 0    0 0   000   0
    ---------------------------------------------------------------------------

    -- Detect if a bit is set in each nibble
    sel1_0(I) <= in_vec(I*8+0) or in_vec(I*8+1) or in_vec(I*8+2) or in_vec(I*8+3);
    sel1_1(I) <= in_vec(I*8+4) or in_vec(I*8+5) or in_vec(I*8+6) or in_vec(I*8+7);
    sel1(I) <= sel1_0(I) or sel1_1(I);

    -- Generate correct two lsb bits for each nibble within these 8 bits
    -- MS nibble
    -- Possible Pos(3 to 4)
    res1_0(I)(0) <= '1' when (in_vec(I*8+0 to I*8+2) = "001") or (in_vec(I*8+0 to I*8+3)= "0001") else '0';
    res1_0(I)(1) <= '1' when (in_vec(I*8+0 to I*8+1) = "01") or (in_vec(I*8+0 to I*8+3) = "0001") else '0';

    -- LS nibble
    -- Possible Pos(3 to 4)
    res1_1(I)(0) <= '1' when (in_vec(I*8+4 to I*8+6) = "001") or (in_vec(I*8+4 to I*8+7)= "0001") else '0';
    res1_1(I)(1) <= '1' when (in_vec(I*8+4 to I*8+5) = "01") or (in_vec(I*8+4 to I*8+7) = "0001") else '0';

    -- Now select the MS nibble if any of it's nibble bits are set
    -- otherwise select the other nibble bits result
    -- Select Possible Pos(3 to 4) from the two above
    res1(I)(1 to 2) <= res1_0(I) when sel1_0(I) = '1' else res1_1(I);

    -- The MSb of the position for these 8 bits should be '0' if the MS nibble bits are set
    -- or '1' if the LS nibble bits are set or '0' if no bits are set
    -- Possible Pos(2)
    res1(I)(0) <= not(sel1_0(I)) and sel1_1(I);
  end generate First_Level;

  -----------------------------------------------------------------------------
  -- Second pass
  -- Find possible Pos(1) bits
  -- Mux appropriate Pos(2-4)
  -----------------------------------------------------------------------------

  -- Select the Pos(2 to 4) from 0-7 if any of the bits wer set
  -- Otherwise select Pos(2 to 4) from bits 8-15
  res2_1(1 to 3) <= res1(0) when sel1(0) = '1' else res1(1);
  -- Possible Pos(1) set if a bit is set in 8-15 but not 0-7
  res2_1(0) <= not(sel1(0)) and sel1(1);
  -- Bit set in 0-15?
  sel2_1 <= sel1(0) or sel1(1);

  -- Select Pos(2 to 4) for bits 16-23 if any of the bits were set
  -- Otherwise Pos(2 to 4) = "000"
  res2_2(1 to 3) <= res1(2) when sel1(2) = '1' else "000";
  -- Possible Pos(1) is set if bit 24 is set, but not bits 16-23
  res2_2(0)      <= not(sel1(2)) and in_vec(24);
  -- Bit set in 16-24?
  sel2_2         <= sel1(2) or in_vec(24);
  
  -----------------------------------------------------------------------------
  -- Last pass
  -- Set Pos(0)
  -- Select appropriate Pos(1-4)
  -----------------------------------------------------------------------------

  -- Use Pos(2-4) from bits 0-15 if a bit was set
  -- Otherwise use Pos(2-4) from bits 16-24
  MEM_Mant_One_Pos(1 to 4) <= res2_1 when sel2_1 = '1' else res2_2;
  -- Pos(0) is set if bits 0-15 are 0, and a bit in 16-24 is set
  MEM_Mant_One_Pos(0) <= not(sel2_1) and sel2_2;

  -- A bit was set (not all zero)
  MEM_Mant_One_Found <= sel2_1 or sel2_2;
                 
end architecture IMP;