exception_registers.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: exception_registers.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- exception_registers.vhd - Entity and architecture
--
--  ***************************************************************************
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--  **  standard level Xilinx Hotline support, and will only address         **
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--
-------------------------------------------------------------------------------
-- Filename:        exception_registers.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              exception_registers.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2004-02-13    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;


entity exception_registers is
  generic (
    C_DATA_SIZE      : natural range 4 to 64 := 64;
    C_FSL_EXCEPTION  : boolean := false;
    C_MAX_FSL_LINKS  : natural
  );
  port (
    Clk                      : in  std_logic;
    Reset                    : in  boolean;
    Clr_ESR                  : in  boolean;
    Load_EAR                 : in  boolean;
    Load_EDR                 : in  boolean;
    Load_ESR                 : in  boolean;
    EX_delayslot_Instr       : in  boolean;
    EX_Branch_Target         : in  std_logic_vector(0 to 31);
    EX_Load_BTR              : in  boolean;
    Unaligned_Exception      : in  std_logic;
    Illegal_Opcode_Exception : in  std_logic;
    IExt_Bus_Exception       : in  std_logic;
    DExt_Bus_Exception       : in  std_logic;
    Div_Zero_Exception       : in  std_logic;
    FPU_Exception            : in  std_logic;
    FSL_Exception            : in  std_logic;
    SW_Instr                 : in  std_logic;
    Word_Access              : in  std_logic;
    Write_Addr               : in  std_logic_vector(0 to 4);
    Data_Addr                : in  std_logic_vector(0 to 31);
    PC_EX                    : in  std_logic_vector(0 to 31);
    EX_Result                : in  std_logic_vector(0 to C_DATA_SIZE-1);
    FSL_No                   : in  natural range 0 to C_MAX_FSL_LINKS-1;  -- Which FSL to operate on
    BTR                      : out BTR_TYPE;
    EAR                      : out EAR_TYPE;
    EDR                      : out EDR_TYPE;
    ESR                      : out ESR_TYPE
    );
end entity exception_registers;

architecture IMP of exception_registers is

  signal reset_ESR : boolean;
  
begin  -- architecture IMP

  EAR_DFF: process (Clk) is
  begin  -- process EAR_DFF
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Reset then                 -- synchronous reset (active true)
        EAR <= (others => '0');
      else
        if (Load_EAR) then
          EAR <= Data_Addr;
        end if;
      end if;
    end if;
  end process EAR_DFF;

  EDR_DFF: process (Clk) is
  begin  -- process EAR_DFF
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Reset then                 -- synchronous reset (active true)
        EDR <= (others => '0');
      else
        if (Load_EDR) then
          EDR <= EX_Result;
        end if;
      end if;
    end if;
  end process EDR_DFF;

  BTR_DFF: process (Clk) is
  begin  -- process BTR_DFF
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Reset then                  -- synchronous reset (active high)
        BTR <= (others => '0');
      elsif (EX_Load_BTR) then
        BTR <= EX_Branch_Target;
      end if;
    end if;
  end process BTR_DFF;

  reset_ESR <= Reset or Clr_ESR;
  
  ESR_DFF : process (Clk) is
  begin  -- process ESR_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if reset_ESR then                     -- synchronous reset (active true)
        ESR <= (others => '0');
      else
        if (Load_ESR) then
          if( EX_delayslot_Instr ) then
            ESR(19)       <= '1';
          else
            ESR(19)       <= '0';
          end if;
          
          -- ESS.
          if( ( C_FSL_EXCEPTION ) and (FSL_Exception = '1') ) then
            ESR(22 to 26) <= std_logic_vector(to_unsigned(FSL_No, 5));
          else
            ESR(22 to 26) <= Write_Addr;
          end if;
          ESR(21)       <= SW_Instr;
          ESR(20)       <= Word_Access;
          
          -- EC.
          ESR(27 to 31) <= (others => '0');
          if (IExt_Bus_Exception = '1') then
            ESR(27 to 31) <= INSTRUCTION_BUS_EXCEPTION_KIND;
          elsif (Illegal_Opcode_Exception = '1') then
            ESR(27 to 31) <= ILLEGAL_OPCODE_EXCEPTION_KIND;            
          elsif (DExt_Bus_Exception = '1') then
            ESR(27 to 31) <= DATA_BUS_EXCEPTION_KIND;            
          elsif (Unaligned_Exception = '1') then
            ESR(27 to 31) <= UNALIGNMENT_EXCEPTION_KIND;            
          elsif (Div_Zero_Exception = '1') then
            ESR(27 to 31) <= DIV_BY_ZERO_EXCEPTION_KIND;            
          elsif (FPU_Exception = '1') then
            ESR(27 to 31) <= FPU_EXCEPTION_KIND;            
          elsif( ( C_FSL_EXCEPTION ) and (FSL_Exception = '1') ) then
            ESR(27 to 31) <= FSL_CTRL_ERR_EXCEPTION_KIND;            
          end if;
        end if;
      end if;
    end if;

  end process ESR_DFF;
end architecture IMP;