📄 dsp_module.vhd
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MASK => to_bitvector(C_MASK), -- [bit_vector] MREG => C_M_REG, -- [integer] MULTCARRYINREG => 0, -- [integer] OPMODEREG => 0, -- [integer] PATTERN => to_bitvector(C_PATTERN), -- [bit_vector] PREG => C_P_REG, -- [integer] SEL_MASK => "MASK", -- [string] SEL_PATTERN => "PATTERN", -- [string] SEL_ROUNDING_MASK => "SEL_MASK", -- [string] USE_MULT => LEGACY_MODE, -- [string] USE_PATTERN_DETECT => C_USE_PATTERN, -- [string] USE_SIMD => "ONE48") -- [string] port map ( ACOUT => open, -- [out std_logic_vector(29 downto 0)] BCOUT => open, -- [out std_logic_vector(17 downto 0)] CARRYCASCOUT => open, -- [out std_ulogic] CARRYOUT => open, -- [out std_logic_vector(3 downto 0)] MULTSIGNOUT => open, -- [out std_ulogic] OVERFLOW => open, -- [out std_ulogic] P => P, -- [out std_logic_vector(47 downto 0)] PATTERNBDETECT => open, -- [out std_ulogic] PATTERNDETECT => DETECT, -- [out std_ulogic] PCOUT => PCOUT, -- [out std_logic_vector(47 downto 0)] UNDERFLOW => open, -- [out std_ulogic] A => A1, -- [in std_logic_vector(29 downto 0)] ACIN => zero30, -- [in std_logic_vector(29 downto 0)] ALUMODE => zero4, -- [in std_logic_vector(3 downto 0)] B => B, -- [in std_logic_vector(17 downto 0)] BCIN => zero18, -- [in std_logic_vector(17 downto 0)] C => C, -- [in std_logic_vector(47 downto 0)] CARRYCASCIN => '0', -- [in std_ulogic] CARRYIN => '0', -- [in std_ulogic] CARRYINSEL => zero3, -- [in std_logic_vector(2 downto 0)] CEA1 => ab_ce_i, -- [in std_ulogic] CEA2 => ab_ce2_i, -- [in std_ulogic] CEALUMODE => '0', -- [in std_ulogic] CEB1 => ab_ce_i, -- [in std_ulogic] CEB2 => ab_ce2_i, -- [in std_ulogic] CEC => '0', -- [in std_ulogic] CECARRYIN => '0', -- [in std_ulogic] CECTRL => '0', -- [in std_ulogic] CEM => m_ce_i, -- [in std_ulogic] CEMULTCARRYIN => '0', -- [in std_ulogic] CEP => p_ce_i, -- [in std_ulogic] CLK => CLK, -- [in std_ulogic] MULTSIGNIN => '0', -- [in std_ulogic] OPMODE => OpMode, -- [in std_logic_vector(6 downto 0)] PCIN => PCIN, -- [in std_logic_vector(47 downto 0)] RSTA => '0', -- [in std_ulogic] RSTALLCARRYIN => '0', -- [in std_ulogic] RSTALUMODE => '0', -- [in std_ulogic] RSTB => '0', -- [in std_ulogic] RSTC => '0', -- [in std_ulogic] RSTCTRL => '0', -- [in std_ulogic] RSTM => Reset_M, -- [in std_ulogic] RSTP => Reset_P); -- [in std_ulogic] end generate Using_Virtex5; Using_Spartan3ADSP : if (C_TARGET = spartan3Adsp) generate subtype virtex_opmode is std_logic_vector(0 to 6); subtype s3adsp_opmode is std_logic_vector(0 to 7); function convert_s3adsp_opmode(v_op : virtex_opmode) return s3adsp_opmode is begin -- function convert_s3adsp_opmode case v_op is when "0000101" => return "00000001"; -- AxB when "0010101" => return "00000101"; -- PCIn + AxB when "1010101" => return "00001101"; -- (PCIN >> 17) + AxB when "0001100" => return "00000111"; -- PCIn + C (for S3ADSP C=D:A:B) when others => return "00000000"; end case; end function convert_s3adsp_opmode; constant s3_opmode : s3adsp_opmode := convert_s3adsp_opmode(C_OpMode); begin Need_to_shift_P_in_fabric : if (C_OpMode = "1010101") generate signal pcin_shifted : std_logic_vector(0 to 47); begin pcin_shifted(0 to 16) <= (others => P_Copy(0)); pcin_shifted(17 to 47) <= P_Copy(0 to 30); DSP48A_I1 : DSP48A generic map ( A0REG => C_AB_REG, -- [integer] A1REG => 0, -- [integer] B0REG => C_AB_REG, -- [integer] B1REG => 0, -- [integer] CARRYINREG => 0, -- [integer] CARRYINSEL => "OPMODE5", -- [string] CREG => 0, -- [integer] DREG => 0, -- [integer] MREG => C_M_REG, -- [integer] OPMODEREG => 0, -- [integer] PREG => C_P_REG, -- [integer] RSTTYPE => "SYNC") -- [string] port map ( BCOUT => open, -- [out std_logic_vector(17 downto 0)] CARRYOUT => open, -- [out std_ulogic] P => P, -- [out std_logic_vector(47 downto 0)] PCOUT => PCOUT, -- [out std_logic_vector(47 downto 0)] A => A, -- [in std_logic_vector(17 downto 0)] B => B, -- [in std_logic_vector(17 downto 0)] C => pcin_shifted, -- [in std_logic_vector(47 downto 0)] CARRYIN => '0', -- [in std_ulogic] CEA => ab_ce2_i, -- [in std_ulogic] CEB => ab_ce2_i, -- [in std_ulogic] CEC => '0', -- [in std_ulogic] CECARRYIN => '0', -- [in std_ulogic] CED => '0', -- [in std_ulogic] CEM => m_ce_i, -- [in std_ulogic] CEOPMODE => '0', -- [in std_ulogic] CEP => p_ce_i, -- [in std_ulogic] CLK => CLK, -- [in std_ulogic] D => zero18, -- [in std_logic_vector(17 downto 0)] OPMODE => s3_opmode, -- [in std_logic_vector(7 downto 0)] PCIN => (others => '0'), -- [in std_logic_vector(47 downto 0)] RSTA => '0', -- [in std_ulogic] RSTB => '0', -- [in std_ulogic] RSTC => '0', -- [in std_ulogic] RSTCARRYIN => '0', -- [in std_ulogic] RSTD => '0', -- [in std_ulogic] RSTM => Reset_M, -- [in std_ulogic] RSTOPMODE => '0', -- [in std_ulogic] RSTP => Reset_P); -- [in std_ulogic] end generate Need_to_shift_P_in_fabric; P_plus_C_Mode: if (C_OpMode = "0001100") generate signal new_C : std_logic_vector(0 to 17); begin new_C <= "000000" & C(0 to 11); DSP48A_I1 : DSP48A generic map ( A0REG => C_AB_REG, -- [integer] A1REG => 0, -- [integer] B0REG => C_AB_REG, -- [integer] B1REG => 0, -- [integer] CARRYINREG => 0, -- [integer] CARRYINSEL => "OPMODE5", -- [string] CREG => 0, -- [integer] DREG => 0, -- [integer] MREG => C_M_REG, -- [integer] OPMODEREG => 0, -- [integer] PREG => C_P_REG, -- [integer] RSTTYPE => "SYNC") -- [string] port map ( BCOUT => open, -- [out std_logic_vector(17 downto 0)] CARRYOUT => open, -- [out std_ulogic] P => P, -- [out std_logic_vector(47 downto 0)] PCOUT => PCOUT, -- [out std_logic_vector(47 downto 0)] A => C(12 to 29), -- [in std_logic_vector(17 downto 0)] B => C(30 to 47), -- [in std_logic_vector(17 downto 0)] C => zero48, -- [in std_logic_vector(47 downto 0)] CARRYIN => '0', -- [in std_ulogic] CEA => ab_ce2_i, -- [in std_ulogic] CEB => ab_ce2_i, -- [in std_ulogic] CEC => '0', -- [in std_ulogic] CECARRYIN => '0', -- [in std_ulogic] CED => '0', -- [in std_ulogic] CEM => m_ce_i, -- [in std_ulogic] CEOPMODE => '0', -- [in std_ulogic] CEP => p_ce_i, -- [in std_ulogic] CLK => CLK, -- [in std_ulogic] D => new_C, -- [in std_logic_vector(17 downto 0)] OPMODE => s3_opmode, -- [in std_logic_vector(7 downto 0)] PCIN => PCIN, -- [in std_logic_vector(47 downto 0)] RSTA => '0', -- [in std_ulogic] RSTB => '0', -- [in std_ulogic] RSTC => '0', -- [in std_ulogic] RSTCARRYIN => '0', -- [in std_ulogic] RSTD => '0', -- [in std_ulogic] RSTM => Reset_M, -- [in std_ulogic] RSTOPMODE => '0', -- [in std_ulogic] RSTP => Reset_P); -- [in std_ulogic] end generate P_plus_C_Mode; Normal_in_fabric : if (C_OpMode /= "1010101") and (C_OpMode /= "0001100") generate DSP48A_I1 : DSP48A generic map ( A0REG => C_AB_REG, -- [integer] A1REG => 0, -- [integer] B0REG => C_AB_REG, -- [integer] B1REG => 0, -- [integer] CARRYINREG => 0, -- [integer] CARRYINSEL => "OPMODE5", -- [string] CREG => 0, -- [integer] DREG => 0, -- [integer] MREG => C_M_REG, -- [integer] OPMODEREG => 0, -- [integer] PREG => C_P_REG, -- [integer] RSTTYPE => "SYNC") -- [string] port map ( BCOUT => open, -- [out std_logic_vector(17 downto 0)] CARRYOUT => open, -- [out std_ulogic] P => P, -- [out std_logic_vector(47 downto 0)] PCOUT => PCOUT, -- [out std_logic_vector(47 downto 0)] A => A, -- [in std_logic_vector(17 downto 0)] B => B, -- [in std_logic_vector(17 downto 0)] C => C, -- [in std_logic_vector(47 downto 0)] CARRYIN => '0', -- [in std_ulogic] CEA => ab_ce2_i, -- [in std_ulogic] CEB => ab_ce2_i, -- [in std_ulogic] CEC => '0', -- [in std_ulogic] CECARRYIN => '0', -- [in std_ulogic] CED => '0', -- [in std_ulogic] CEM => m_ce_i, -- [in std_ulogic] CEOPMODE => '0', -- [in std_ulogic] CEP => p_ce_i, -- [in std_ulogic] CLK => CLK, -- [in std_ulogic] D => zero18, -- [in std_logic_vector(17 downto 0)] OPMODE => s3_opmode, -- [in std_logic_vector(7 downto 0)] PCIN => PCIN, -- [in std_logic_vector(47 downto 0)] RSTA => '0', -- [in std_ulogic] RSTB => '0', -- [in std_ulogic] RSTC => '0', -- [in std_ulogic] RSTCARRYIN => '0', -- [in std_ulogic] RSTD => '0', -- [in std_ulogic] RSTM => Reset_M, -- [in std_ulogic] RSTOPMODE => '0', -- [in std_ulogic] RSTP => Reset_P); -- [in std_ulogic] end generate Normal_in_fabric; end generate Using_Spartan3ADSP;end architecture IMP;⌨️ 快捷键说明
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