dsp_module.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: dsp_module.vhd,v 1.2 2007/10/31 14:22:52 stefana Exp $
-------------------------------------------------------------------------------
-- dsp_module.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
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--  **  standard level Xilinx Hotline support, and will only address         **
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--
-------------------------------------------------------------------------------
-- Filename:        dsp_module.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:   
--              dsp_module.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.2 $
-- Date:            $Date: 2007/10/31 14:22:52 $
--
-- History:
--   goran  2006-08-21    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

library unisim;
use unisim.vcomponents.all;

entity dsp_module is
  generic (
    C_TARGET      : TARGET_FAMILY_TYPE;
    C_A_WIDTH     : natural                   := 18;
    C_B_WIDTH     : natural                   := 18;
    C_P_WIDTH     : natural                   := 48;
    C_AB_REG      : integer;
    C_M_REG       : integer;
    C_P_REG       : integer;
    C_OPMODE      : std_logic_vector(0 to 6)  := (others => '0');  --Only for DSP48A
    C_PATTERN     : std_logic_vector(0 to 47) := (others => '1');  --Only for DSP48E
    C_MASK        : std_logic_vector(0 to 47) := (others => '1');  --Only for DSP48E
    C_USE_PATTERN : string                    := "NO_PATDET");
  port (
    Clk     : in  std_logic;
    Reset_P : in  std_logic;
    Reset_M : in  std_logic;
    AB_CE   : in  std_logic;
    M_CE    : in  std_logic;
    P_CE    : in  std_logic;
    OpMode  : in  std_logic_vector(0 to 6);
    A       : in  std_logic_vector(0 to C_A_WIDTH-1);
    B       : in  std_logic_vector(0 to C_B_WIDTH-1);
    C       : in  std_logic_vector(0 to C_P_WIDTH-1);    
    P       : out std_logic_vector(0 to C_P_WIDTH-1);
    P_Copy  : in  std_logic_vector(0 to C_P_WIDTH-1);
    PCIN    : in  std_logic_vector(0 to C_P_WIDTH-1);
    PCOUT   : out std_logic_vector(0 to C_P_WIDTH-1);
    DETECT  : out std_logic
    );
end entity dsp_module;

architecture IMP of dsp_module is

  function legacy_mode_calc return string is
  begin  -- function legacy_mode_calc
    if (C_TARGET = VIRTEX4) then
      if (C_M_REG = 0) then
        return "MULT18X18";
      else
        return "MULT18X18S";
      end if;
    else
      if (C_M_REG = 0) then
        return "MULT";
      else
        return "MULT_S";
      end if;
    end if;
  end function legacy_mode_calc;

  constant LEGACY_MODE : string := legacy_mode_calc;

  signal zero3  : std_logic_vector(0 to 2);
  signal zero4  : std_logic_vector(0 to 3);
  signal zero18 : std_logic_vector(0 to 17);
  signal zero30 : std_logic_vector(0 to 29);
  signal zero48 : std_logic_vector(0 to 47);

  signal ab_ce_i  : std_logic;
  signal ab_ce2_i : std_logic;
  signal m_ce_i   : std_logic;
  signal p_ce_i   : std_logic;
  
begin  -- architecture IMP


  ab_ce_i  <= AB_CE when C_AB_REG > 0 else '0';
  ab_ce2_i <= AB_CE when C_AB_REG = 1 else '0';
  m_ce_i   <= M_CE  when C_M_REG /= 0 else '0';
  p_ce_i   <= P_CE  when C_P_REG /= 0 else '0';
  
  
  zero3  <= (others => '0');
  zero4  <= (others => '0');
  zero18 <= (others => '0');
  zero30 <= (others => '0');
  zero48 <= (others => '0');

  Using_Virtex4 : if (C_TARGET = VIRTEX4) generate

    DSP48_I1 : DSP48
      generic map (
        AREG          => C_AB_REG,      -- [integer]
        B_INPUT       => "DIRECT",      -- [string]
        BREG          => C_AB_REG,      -- [integer]
        CARRYINREG    => 0,             -- [integer]
        CARRYINSELREG => 0,             -- [integer]
        CREG          => 0,             -- [integer]
        LEGACY_MODE   => LEGACY_MODE,   -- [string]
        MREG          => C_M_REG,       -- [integer]
        OPMODEREG     => 0,             -- [integer]
        PREG          => C_P_REG,       -- [integer]
        SUBTRACTREG   => 0)             -- [integer]
      port map (
        BCOUT => open,                  -- [out std_logic_vector(17 downto 0)]
        P     => P,                     -- [out std_logic_vector(47 downto 0)]
        PCOUT => PCOUT,                 -- [out std_logic_vector(47 downto 0)]

        A          => A,                -- [in  std_logic_vector(17 downto 0)]
        B          => B,                -- [in  std_logic_vector(17 downto 0)]
        BCIN       => zero18,           -- [in  std_logic_vector(17 downto 0)]
        C          => C,                -- [in  std_logic_vector(47 downto 0)]
        CARRYIN    => '0',              -- [in  std_ulogic]
        CARRYINSEL => "00",             -- [in  std_logic_vector(1 downto 0)]
        CEA        => ab_ce_i,          -- [in  std_ulogic]
        CEB        => ab_ce_i,          -- [in  std_ulogic]
        CEC        => '0',              -- [in  std_ulogic]
        CECARRYIN  => '0',              -- [in  std_ulogic]
        CECINSUB   => '0',              -- [in  std_ulogic]
        CECTRL     => '0',              -- [in  std_ulogic]
        CEM        => m_ce_i,           -- [in  std_ulogic]
        CEP        => p_ce_i,           -- [in  std_ulogic]
        CLK        => CLK,              -- [in  std_ulogic]
        OPMODE     => OpMode,           -- [in  std_logic_vector(6 downto 0)]
        PCIN       => PCIN,             -- [in  std_logic_vector(47 downto 0)]
        RSTA       => '0',              -- [in  std_ulogic]
        RSTB       => '0',              -- [in  std_ulogic]
        RSTC       => '0',              -- [in  std_ulogic]
        RSTCARRYIN => '0',              -- [in  std_ulogic]
        RSTCTRL    => '0',              -- [in  std_ulogic]
        RSTM       => Reset_M,          -- [in  std_ulogic]
        RSTP       => Reset_P,          -- [in  std_ulogic]
        SUBTRACT   => '0');             -- [in std_ulogic]

    
  end generate Using_Virtex4;

  Using_Virtex5 : if (C_TARGET = VIRTEX5) generate
    signal A1 : std_logic_vector(0 to 29);
  begin
    
    Fill_A : process (A) is
    begin  -- process Fill_A
      A1(30-C_A_WIDTH to 29) <= A;
      if (C_A_WIDTH < 30) then
        A1(0 to 29-C_A_WIDTH) <= (others => A(0));
      end if;
    end process Fill_A;

    DSP48E_I1 : DSP48E
      generic map (
        ACASCREG                        => C_AB_REG,         -- [integer]
        ALUMODEREG                      => 0,                -- [integer]
        AREG                            => C_AB_REG,         -- [integer]
        AUTORESET_PATTERN_DETECT        => false,            -- [boolean]
        AUTORESET_PATTERN_DETECT_OPTINV => "MATCH",          -- [string]
        A_INPUT                         => "DIRECT",         -- [string]
        BCASCREG                        => C_AB_REG,         -- [integer]
        BREG                            => C_AB_REG,         -- [integer]
        B_INPUT                         => "DIRECT",         -- [string]
        CARRYINREG                      => 0,                -- [integer]
        CARRYINSELREG                   => 0,                -- [integer]
        CREG                            => 0,                -- [integer]