msr_reg_bit.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: msr_reg_bit.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- MSR_Reg_Bit - entity/architecture
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        msr_reg_bit.vhd
-- Version:         v1.00a
-- Description:     Implements 1 bit of the MSR register
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              msr_reg_bit.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;
library Unisim;
use Unisim.vcomponents.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity MSR_Reg_Bit is
  generic (
    -- Size generics
    C_TARGET : TARGET_FAMILY_TYPE);
  port (
    Clk   : in std_logic;
    -- Reset : in boolean;

    Write_MSR : in  std_logic;
    New_Value : in  std_logic;
    MSR_Rst   : in  std_logic;
    MSR_Set   : in  std_logic;
    MSR       : out std_logic
    );

end entity MSR_Reg_Bit;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of MSR_Reg_Bit is
  
begin  -- architecture IMP

  MSR_I : FDRSE
    port map (
      Q  => MSR,                        -- [out std_logic]
      C  => Clk,                        -- [in  std_logic]
      CE => Write_MSR,                  -- [in  std_logic]
      D  => New_Value,                  -- [in  std_logic]
      R  => MSR_Rst,                    -- [in  std_logic]
      S  => MSR_Set);                   -- [in std_logic]

end architecture IMP;