ram_module.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

      signal web_i  : std_logic_vector(0 to 3);
      signal dib_i  : std_logic_vector(0 to 31);
      signal dibp_i : std_logic_vector(0 to 3);
      signal dob_i  : std_logic_vector(0 to 31);
      signal dobp_i : std_logic_vector(0 to 3);
    begin

      wea_i                     <= (others => WEA(I));
      dia_i                     <= "000000000000000000000000" & data_ina_i(I*8 to I*8+7);
      diap_i                    <= "000" & data_inpa_i(I);
      data_outa_i(I*8 to I*8+7) <= doa_i(24 to 31);
      data_outpa_i(I)           <= doap_i(3);

      web_i                     <= (others => WEB(I));
      dib_i                     <= "000000000000000000000000" & data_inb_i(I*8 to I*8+7);
      dibp_i                    <= "000" & data_inpb_i(I);
      data_outb_i(I*8 to I*8+7) <= dob_i(24 to 31);
      data_outpb_i(I)           <= dobp_i(3);

      RAMB36_I1 : RAMB36
        generic map (
          DOA_REG             => 0,               -- [integer]
          DOB_REG             => 0,               -- [integer]
          RAM_EXTENSION_A     => "NONE",          -- [string]
          RAM_EXTENSION_B     => "NONE",          -- [string]
          READ_WIDTH_A        => 9,               -- [integer]
          READ_WIDTH_B        => 9,               -- [integer]
          SIM_COLLISION_CHECK => sim_check_mode,  -- [string]
          WRITE_MODE_A        => write_mode,      -- [string]
          WRITE_MODE_B        => write_mode,      -- [string]
          WRITE_WIDTH_A       => 9,               -- [integer]
          WRITE_WIDTH_B       => 9)               -- [integer]
        port map (
          CLKA => CLKA,                           -- [in              
          ENA  => ENA,                            -- [in  std_ulogic]

          ADDRA          => addra_i,    -- [in  std_logic_vector(15 downto 0)]
          WEA            => wea_i,      -- [in  std_logic_vector(3 downto 0)]
          DIA            => dia_i,      -- [in  std_logic_vector (31 downto 0)]
          DIPA           => diap_i,     -- [in  std_logic_vector (3 downto 0)]
          DOA            => doa_i,      -- [out std_logic_vector (31 downto 0)]
          DOPA           => doap_i,     -- [out std_logic_vector (3 downto 0)]
          SSRA           => '0',        -- [in  std_ulogic]
          REGCEA         => '1',        -- [in  std_ulogic]
          CASCADEOUTLATA => open,       -- [out std_ulogic]
          CASCADEINLATA  => '0',        -- [in  std_ulogic]
          CASCADEINREGA  => '0',        -- [in  std_ulogic]
          CASCADEOUTREGA => open,       -- [out std_ulogic]

          CLKB => CLKB,                 -- [in  std_ulogic]            
          ENB  => ENB,                  -- [in  std_ulogic]

          ADDRB          => addrb_i,    -- [in  std_logic_vector(15 downto 0)]
          WEB            => web_i,      -- [in std_logic_vector(3 downto 0)]
          DIB            => dib_i,      -- [in  std_logic_vector (31 downto 0)]
          DIPB           => dibp_i,     -- [in  std_logic_vector (3 downto 0)]
          DOB            => dob_i,      -- [out std_logic_vector (31 downto 0)]
          DOPB           => dobp_i,     -- [out std_logic_vector (3 downto 0)]
          SSRB           => '0',        -- [in  std_ulogic]
          REGCEB         => '1',        -- [in  std_ulogic]
          CASCADEOUTLATB => open,       -- [out std_ulogic]
          CASCADEINLATB  => '0',        -- [in  std_ulogic]
          CASCADEINREGB  => '0',        -- [in  std_ulogic]
          CASCADEOUTREGB => open);      -- [out std_ulogic]
    end generate The_BRAMs;
  end generate Using_B36_S9;

  Using_B16_S9 : if (What_BRAM.What_Kind = B16_S9) generate
    -- Write enables is tied one for each bram block
    The_BRAMs : for I in 0 to nr_of_brams-1 generate
      RAMB16_S9_1 : RAMB16_S9_S9
        generic map (
          SIM_COLLISION_CHECK => sim_check_mode,
          WRITE_MODE_A        => write_mode,
          WRITE_MODE_B        => write_mode
          )
        port map (
                                        -- Port A
          CLKA  => CLKA,                -- [in  std_ulogic]
          ENA   => ENA,                 -- [in  std_ulogic]
          WEA   => WEA(I),              -- [in  std_ulogic]
          DIA   => data_ina_i(I*8 to I*8+7),  -- [in  std_logic_vector (7 downto 0)]
          DIPA  => data_inpa_i(I to I),  -- [in  std_logic_vector (0 downto 0)]
          ADDRA => addra_i,             -- [in  std_logic_vector (10 downto 0)]
          DOA   => data_outa_i(I*8 to I*8+7),  -- [out std_logic_vector (7 downto 0)]
          DOPA  => data_outpa_i(I to I),  -- [out std_logic_vector (0 downto 0)]
          SSRA  => '0',                 -- [in  std_ulogic]
          -- Port B
          CLKB  => CLKB,                -- [in  std_ulogic]
          ENB   => ENB,                 -- [in  std_ulogic]
          WEB   => WEB(I),              -- [in  std_ulogic]
          DIB   => data_inb_i(I*8 to I*8+7),  -- [in  std_logic_vector (7 downto 0)]
          DIPB  => data_inpb_i(I to I),  -- [in  std_logic_vector (0 downto 0)]
          ADDRB => addrb_i,             -- [in  std_logic_vector (10 downto 0)]
          DOB   => data_outb_i(I*8 to I*8+7),  -- [out std_logic_vector (7 downto 0)]
          DOPB  => data_outpb_i(I to I),  -- [out std_logic_vector (0 downto 0)]
          SSRB  => '0'                  -- [in  std_ulogic]
          );
    end generate The_BRAMs;
  end generate Using_B16_S9;


  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  --  BRAM organizaed as x4
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------

  Using_B36_S4 : if (What_BRAM.What_Kind = B36_S4) generate
    signal addra_i : std_logic_vector(15 downto 0);
    signal addrb_i : std_logic_vector(15 downto 0);
  begin

    Pad_RAMB36_Addresses : process (ADDRA, ADDRB) is
      begin  -- process Pad_RAMB36_Addresses
        addra_i                            <= (others => '0');
                                        -- Address bit 15 is only used when BRAM are cascaded
        addra_i(14 downto 15-C_ADDR_WIDTH) <= ADDRA;
        addrb_i                            <= (others => '0');
                                        -- Address bit 15 is only used when BRAM are cascaded
        addrb_i(14 downto 15-C_ADDR_WIDTH) <= ADDRB;
    end process Pad_RAMB36_Addresses;

    The_BRAMs : for I in 0 to nr_of_brams-1 generate
      signal wea_i  : std_logic_vector(0 to 3);
      signal dia_i  : std_logic_vector(0 to 31);
      signal diap_i : std_logic_vector(0 to 3);
      signal doa_i  : std_logic_vector(0 to 31);
      signal doap_i : std_logic_vector(0 to 3);
      signal web_i  : std_logic_vector(0 to 3);
      signal dib_i  : std_logic_vector(0 to 31);
      signal dibp_i : std_logic_vector(0 to 3);
      signal dob_i  : std_logic_vector(0 to 31);
      signal dobp_i : std_logic_vector(0 to 3);
    begin

      wea_i                     <= (others => WEA(I/2));
      dia_i                     <= "0000000000000000000000000000" & data_ina_i(I*4 to I*4+3);
      diap_i                    <= "0000";
      data_outa_i(I*4 to I*4+3) <= doa_i(28 to 31);

      web_i                     <= (others => WEB(I/2));
      dib_i                     <= "0000000000000000000000000000" & data_inb_i(I*4 to I*4+3);
      dibp_i                    <= "0000";
      data_outb_i(I*4 to I*4+3) <= dob_i(28 to 31);

      RAMB36_I1 : RAMB36
        generic map (
          DOA_REG             => 0,               -- [integer]
          DOB_REG             => 0,               -- [integer]
          RAM_EXTENSION_A     => "NONE",          -- [string]
          RAM_EXTENSION_B     => "NONE",          -- [string]
          READ_WIDTH_A        => 4,               -- [integer]
          READ_WIDTH_B        => 4,               -- [integer]
          SIM_COLLISION_CHECK => sim_check_mode,  -- [string]
          WRITE_MODE_A        => write_mode,      -- [string]
          WRITE_MODE_B        => write_mode,      -- [string]
          WRITE_WIDTH_A       => 4,               -- [integer]
          WRITE_WIDTH_B       => 4)               -- [integer]
        port map (
          CLKA => CLKA,                           -- [in              
          ENA  => ENA,                            -- [in  std_ulogic]

          ADDRA          => addra_i,    -- [in  std_logic_vector(15 downto 0)]
          WEA            => wea_i,      -- [in  std_logic_vector(3 downto 0)]
          DIA            => dia_i,      -- [in  std_logic_vector (31 downto 0)]
          DIPA           => diap_i,     -- [in  std_logic_vector (3 downto 0)]
          DOA            => doa_i,      -- [out std_logic_vector (31 downto 0)]
          DOPA           => open,       -- [out std_logic_vector (3 downto 0)]
          SSRA           => '0',        -- [in  std_ulogic]
          REGCEA         => '1',        -- [in  std_ulogic]
          CASCADEOUTLATA => open,       -- [out std_ulogic]
          CASCADEINLATA  => '0',        -- [in  std_ulogic]
          CASCADEINREGA  => '0',        -- [in  std_ulogic]
          CASCADEOUTREGA => open,       -- [out std_ulogic]

          CLKB => CLKB,                 -- [in  std_ulogic]            
          ENB  => ENB,                  -- [in  std_ulogic]

          ADDRB          => addrb_i,    -- [in  std_logic_vector(15 downto 0)]
          WEB            => web_i,      -- [in std_logic_vector(3 downto 0)]
          DIB            => dib_i,      -- [in  std_logic_vector (31 downto 0)]
          DIPB           => dibp_i,     -- [in  std_logic_vector (3 downto 0)]
          DOB            => dob_i,      -- [out std_logic_vector (31 downto 0)]
          DOPB           => open,       -- [out std_logic_vector (3 downto 0)]
          SSRB           => '0',        -- [in  std_ulogic]
          REGCEB         => '1',        -- [in  std_ulogic]
          CASCADEOUTLATB => open,       -- [out std_ulogic]
          CASCADEINLATB  => '0',        -- [in  std_ulogic]
          CASCADEINREGB  => '0',        -- [in  std_ulogic]
          CASCADEOUTREGB => open);      -- [out std_ulogic]
    end generate The_BRAMs;
  end generate Using_B36_S4;

  Using_B16_S4 : if (What_BRAM.What_Kind = B16_S4) generate
    -- Write enables is tied one for each two bram block (to support byte enables)
    The_BRAMs : for I in 0 to nr_of_brams-1 generate
      RAMB16_S4_1 : RAMB16_S4_S4
        generic map (
          SIM_COLLISION_CHECK => sim_check_mode,
          WRITE_MODE_A        => write_mode,
          WRITE_MODE_B        => write_mode)
        port map (
                                        -- Port A
          CLKA  => CLKA,                -- [in  std_ulogic]
          ENA   => ENA,                 -- [in  std_ulogic]
          WEA   => WEA(I/2),            -- [in  std_ulogic]
          DIA   => data_ina_i(I*4 to I*4+3),  -- [in  std_logic_vector (3 downto 0)]
          ADDRA => addra_i,             -- [in  std_logic_vector (11 downto 0)]
          DOA   => data_outa_i(I*4 to I*4+3),  -- [out std_logic_vector (3 downto 0)]
          SSRA  => '0',                 -- [in  std_ulogic]
          -- Port B
          CLKB  => CLKB,                -- [in  std_ulogic]
          ENB   => ENB,                 -- [in  std_ulogic]
          WEB   => WEB(I/2),            -- [in  std_ulogic]
          DIB   => data_inb_i(I*4 to I*4+3),  -- [in  std_logic_vector (3 downto 0)]
          ADDRB => addrb_i,             -- [in  std_logic_vector (11 downto 0)]
          DOB   => data_outb_i(I*4 to I*4+3),  -- [out std_logic_vector (3 downto 0)]
          SSRB  => '0'                  -- [in  std_ulogic]
          );
    end generate The_BRAMs;
  end generate Using_B16_S4;

  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  --  BRAM organizaed as x2
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------

  Using_B36_S2 : if (What_BRAM.What_Kind = B36_S2) generate