ram_module.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

      end generate The_BRAMs;

    end generate Using_S36_Virtex5;

    Using_S18_Virtex4 : if (C_TARGET = VIRTEX4) generate
      signal wea_i   : std_logic_vector(0 to 3);
      signal web_i   : std_logic_vector(0 to 3);
      signal addra_i : std_logic_vector(14 downto 0);
      signal addrb_i : std_logic_vector(14 downto 0);
    begin

      Pad_RAMB16_Signals : process (ADDRA, ADDRB, WEA, WEB) is
      begin  -- process Pad_RAMB16_Signals
        wea_i                              <= (others => '0');
        wea_i(WEA'range)                   <= WEA;
        addra_i                            <= (others => '0');
        addra_i(13 downto 14-C_ADDR_WIDTH) <= ADDRA;
        web_i                              <= (others => '0');
        web_i(WEB'range)                   <= WEB;
        addrb_i                            <= (others => '0');
        addrb_i(13 downto 14-C_ADDR_WIDTH) <= ADDRB;
      end process Pad_RAMB16_Signals;

      The_BRAMs : for I in 0 to nr_of_brams-1 generate
        signal wea_ii : std_logic_vector(0 to 3);
        signal dia_i  : std_logic_vector(0 to 31);
        signal diap_i : std_logic_vector(0 to 3);
        signal doa_i  : std_logic_vector(0 to 31);
        signal doap_i : std_logic_vector(0 to 3);
        signal web_ii : std_logic_vector(0 to 3);
        signal dib_i  : std_logic_vector(0 to 31);
        signal dibp_i : std_logic_vector(0 to 3);
        signal dob_i  : std_logic_vector(0 to 31);
        signal dobp_i : std_logic_vector(0 to 3);
      begin

        wea_ii                       <= wea_i(I*2 to I*2+1) & wea_i(I*2 to I*2+1);
        dia_i                        <= "0000000000000000" & data_ina_i(I*16 to I*16+15);
        diap_i                       <= "00" & data_inpa_i(I*2 to I*2+1);
        data_outa_i(I*16 to I*16+15) <= doa_i(16 to 31);
        data_outpa_i(I*2 to I*2+1)   <= doap_i(2 to 3);
        web_ii                       <= web_i(I*2 to I*2+1) & web_i(I*2 to I*2+1);
        dib_i                        <= "0000000000000000" & data_inb_i(I*16 to I*16+15);
        dibp_i                       <= "00" & data_inpb_i(I*2 to I*2+1);
        data_outb_i(I*16 to I*16+15) <= dob_i(16 to 31);
        data_outpb_i(I*2 to I*2+1)   <= dobp_i(2 to 3);


        RAMB16_I1 : RAMB16
          generic map (
            READ_WIDTH_A        => 18,  -- [integer]
            READ_WIDTH_B        => 18,  -- [integer]
            WRITE_WIDTH_A       => 18,  -- [integer]
            WRITE_WIDTH_B       => 18,
            SIM_COLLISION_CHECK => sim_check_mode,
            WRITE_MODE_A        => write_mode,
            WRITE_MODE_B        => write_mode
            )                           -- [integer]
          port map (
                                        -- Port A
            CLKA        => CLKA,        -- [in  std_ulogic]
            ADDRA       => addra_i,     -- [in  std_logic_vector (14 downto 0)]
            ENA         => ENA,         -- [in  std_ulogic]
            WEA         => wea_ii,      -- [in  std_logic_vector (3 downto 0)]
            DIA         => dia_i,       -- [in  std_logic_vector (31 downto 0)]
            DIPA        => diap_i,      -- [in  std_logic_vector (3 downto 0)]
            DOA         => doa_i,       -- [out std_logic_vector (31 downto 0)]
            DOPA        => doap_i,      -- [out std_logic_vector (3 downto 0)]
            SSRA        => '0',         -- [in  std_ulogic]
            REGCEA      => '1',         -- [in  std_ulogic]
            CASCADEOUTA => open,        -- [out std_ulogic]
            CASCADEINA  => '0',         -- [in  std_ulogic]

                                        -- Port B
            CLKB        => CLKB,        -- [in  std_ulogic]
            ADDRB       => addrb_i,     -- [in  std_logic_vector (14 downto 0)]
            ENB         => ENB,         -- [in  std_ulogic]
            WEB         => web_ii,      -- [in  std_logic_vector (3 downto 0)]
            DIB         => dib_i,       -- [in  std_logic_vector (31 downto 0)]
            DIPB        => dibp_i,      -- [in  std_logic_vector (3 downto 0)]
            DOB         => dob_i,       -- [out std_logic_vector (31 downto 0)]
            DOPB        => dobp_i,      -- [out std_logic_vector (3 downto 0)]
            SSRB        => '0',         -- [in  std_ulogic]
            REGCEB      => '1',         -- [in  std_ulogic]
            CASCADEOUTB => open,        -- [out std_ulogic]
            CASCADEINB  => '0'          -- [in  std_ulogic]
            );
      end generate The_BRAMs;
    end generate Using_S18_Virtex4;

    Using_S18_Spartan3A : if (C_TARGET = SPARTAN3A)    or
                             (C_TARGET = SPARTAN3AN)   or
                             (C_TARGET = SPARTAN3Adsp) generate
      signal wea_i   : std_logic_vector(0 to 3);
      signal web_i   : std_logic_vector(0 to 3);
      signal addra_i : std_logic_vector(13 downto 0);
      signal addrb_i : std_logic_vector(13 downto 0);
    begin

      Pad_RAMB16_Signals : process (ADDRA, ADDRB, WEA, WEB) is
      begin  -- process Pad_RAMB16_Signals
        wea_i                              <= (others => '0');
        wea_i(WEA'range)                   <= WEA;
        addra_i                            <= (others => '0');
        addra_i(13 downto 14-C_ADDR_WIDTH) <= ADDRA;
        web_i                              <= (others => '0');
        web_i(WEB'range)                   <= WEB;
        addrb_i                            <= (others => '0');
        addrb_i(13 downto 14-C_ADDR_WIDTH) <= ADDRB;
      end process Pad_RAMB16_Signals;

      The_BRAMs : for I in 0 to nr_of_brams-1 generate
        signal wea_ii : std_logic_vector(0 to 3);
        signal dia_i  : std_logic_vector(0 to 31);
        signal diap_i : std_logic_vector(0 to 3);
        signal doa_i  : std_logic_vector(0 to 31);
        signal doap_i : std_logic_vector(0 to 3);
        signal web_ii : std_logic_vector(0 to 3);
        signal dib_i  : std_logic_vector(0 to 31);
        signal dibp_i : std_logic_vector(0 to 3);
        signal dob_i  : std_logic_vector(0 to 31);
        signal dobp_i : std_logic_vector(0 to 3);
      begin

        wea_ii                       <= wea_i(I*2 to I*2+1) & wea_i(I*2 to I*2+1);
        dia_i                        <= "0000000000000000" & data_ina_i(I*16 to I*16+15);
        diap_i                       <= "00" & data_inpa_i(I*2 to I*2+1);
        data_outa_i(I*16 to I*16+15) <= doa_i(16 to 31);
        data_outpa_i(I*2 to I*2+1)   <= doap_i(2 to 3);
        web_ii                       <= web_i(I*2 to I*2+1) & web_i(I*2 to I*2+1);
        dib_i                        <= "0000000000000000" & data_inb_i(I*16 to I*16+15);
        dibp_i                       <= "00" & data_inpb_i(I*2 to I*2+1);
        data_outb_i(I*16 to I*16+15) <= dob_i(16 to 31);
        data_outpb_i(I*2 to I*2+1)   <= dobp_i(2 to 3);


        RAMB16BWE_I1 : RAMB16BWE
          generic map (
            DATA_WIDTH_A        => 18,  -- [integer]
            DATA_WIDTH_B        => 18,  -- [integer]
            SIM_COLLISION_CHECK => sim_check_mode,
            WRITE_MODE_A        => write_mode,
            WRITE_MODE_B        => write_mode
            )                           -- [integer]
          port map (
                                        -- Port A
            CLKA  => CLKA,              -- [in  std_ulogic]
            ADDRA => addra_i,           -- [in  std_logic_vector (13 downto 0)]
            ENA   => ENA,               -- [in  std_ulogic]
            WEA   => wea_ii,            -- [in  std_logic_vector (3 downto 0)]
            DIA   => dia_i,             -- [in  std_logic_vector (31 downto 0)]
            DIPA  => diap_i,            -- [in  std_logic_vector (3 downto 0)]
            DOA   => doa_i,             -- [out std_logic_vector (31 downto 0)]
            DOPA  => doap_i,            -- [out std_logic_vector (3 downto 0)]
            SSRA  => '0',               -- [in  std_ulogic]

                                        -- Port B
            CLKB  => CLKB,              -- [in  std_ulogic]
            ADDRB => addrb_i,           -- [in  std_logic_vector (13 downto 0)]
            ENB   => ENB,               -- [in  std_ulogic]
            WEB   => web_ii,            -- [in  std_logic_vector (3 downto 0)]
            DIB   => dib_i,             -- [in  std_logic_vector (31 downto 0)]
            DIPB  => dibp_i,            -- [in  std_logic_vector (3 downto 0)]
            DOB   => dob_i,             -- [out std_logic_vector (31 downto 0)]
            DOPB  => dobp_i,            -- [out std_logic_vector (3 downto 0)]
            SSRB  => '0'                -- [in  std_ulogic]
            );
      end generate The_BRAMs;
    end generate Using_S18_Spartan3A;


    Not_Using_Byte_Enable_BRAM16 : if (not byte_enable_bram_arch) generate

      -- Write enables is tied one for each bram block
      The_BRAMs : for I in 0 to nr_of_brams-1 generate
        RAMB16_S18_1 : RAMB16_S18_S18
          generic map (
            SIM_COLLISION_CHECK => sim_check_mode,
            WRITE_MODE_A        => write_mode,
            WRITE_MODE_B        => write_mode
            )
          port map (
                                        -- Port A
            CLKA  => CLKA,              -- [in  std_ulogic]
            ENA   => ENA,               -- [in  std_ulogic]
            WEA   => WEA(I),            -- [in  std_ulogic]
            DIA   => data_ina_i(I*16 to I*16+15),  -- [in  std_logic_vector (15 downto 0)]
            DIPA  => data_inpa_i(I*2 to I*2+1),  -- [in  std_logic_vector (1 downto 0)]
            ADDRA => addra_i,           -- [in  std_logic_vector ( 9 downto 0)]
            DOA   => data_outa_i(I*16 to I*16+15),  -- [out std_logic_vector (15 downto 0)]
            DOPA  => data_outpa_i(I*2 to I*2+1),  -- [out std_logic_vector ( 1 downto 0)]
            SSRA  => '0',               -- [in  std_ulogic]
                                        -- Port B
            CLKB  => CLKB,              -- [in  std_ulogic]
            ENB   => ENB,               -- [in  std_ulogic]
            WEB   => WEB(I),            -- [in  std_ulogic]
            DIB   => data_inb_i(I*16 to I*16+15),  -- [in  std_logic_vector (15 downto 0)]
            DIPB  => data_inpb_i(I*2 to I*2+1),  -- [in  std_logic_vector (1 downto 0)]
            ADDRB => addrb_i,           -- [in  std_logic_vector ( 9 downto 0)]
            DOB   => data_outb_i(I*16 to I*16+15),  -- [out std_logic_vector (15 downto 0)]
            DOPB  => data_outpb_i(I*2 to I*2+1),  -- [out std_logic_vector ( 1 downto 0)]
            SSRB  => '0'                -- [in  std_ulogic]
            );
      end generate The_BRAMs;
    end generate Not_Using_Byte_Enable_BRAM16;
  end generate Using_B16_S18;

  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  --  BRAM organizaed as x9
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------

  Using_B36_S9 : if (What_BRAM.What_Kind = B36_S9) generate
    signal addra_i : std_logic_vector(15 downto 0);
    signal addrb_i : std_logic_vector(15 downto 0);
  begin

    Pad_RAMB36_Addresses : process (ADDRA, ADDRB) is
      begin  -- process Pad_RAMB36_Addresses
        addra_i                            <= (others => '0');
                                        -- Address bit 15 is only used when BRAM are cascaded
        addra_i(14 downto 15-C_ADDR_WIDTH) <= ADDRA;
        addrb_i                            <= (others => '0');
                                        -- Address bit 15 is only used when BRAM are cascaded
        addrb_i(14 downto 15-C_ADDR_WIDTH) <= ADDRB;
    end process Pad_RAMB36_Addresses;


    The_BRAMs : for I in 0 to nr_of_brams-1 generate
      signal wea_i  : std_logic_vector(0 to 3);
      signal dia_i  : std_logic_vector(0 to 31);
      signal diap_i : std_logic_vector(0 to 3);
      signal doa_i  : std_logic_vector(0 to 31);
      signal doap_i : std_logic_vector(0 to 3);