ram_module.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

        addrb_i                            <= (others => '0');
                                        -- Address bit 14 is only used when BRAM are cascaded
        addrb_i(13 downto 14-C_ADDR_WIDTH) <= ADDRB;
      end process Pad_RAMB16_Signals;

      RAMB16_I1 : RAMB16
        generic map (
          READ_WIDTH_A        => 36,    -- [integer]
          READ_WIDTH_B        => 36,    -- [integer]
          WRITE_WIDTH_A       => 36,    -- [integer]
          WRITE_WIDTH_B       => 36,
          SIM_COLLISION_CHECK => sim_check_mode,
          WRITE_MODE_A        => write_mode,
          WRITE_MODE_B        => write_mode
          )                             -- [integer]
        port map (
                                        -- Port A
          CLKA        => CLKA,          -- [in  std_ulogic]
          ADDRA       => addra_i,       -- [in  std_logic_vector (14 downto 0)]
          ENA         => ENA,           -- [in  std_ulogic]
          WEA         => wea_i,         -- [in  std_logic_vector (3 downto 0)]
          DIA         => data_ina_i,    -- [in  std_logic_vector (31 downto 0)]
          DIPA        => data_inpa_i,   -- [in  std_logic_vector (3 downto 0)]
          DOA         => data_outa_i,   -- [out std_logic_vector (31 downto 0)]
          DOPA        => data_outpa_i,  -- [out std_logic_vector (3 downto 0)]
          SSRA        => '0',           -- [in  std_ulogic]
          REGCEA      => '1',           -- [in  std_ulogic]
          CASCADEOUTA => open,          -- [out std_ulogic]
          CASCADEINA  => '0',           -- [in  std_ulogic]

                                        -- Port B
          CLKB        => CLKB,          -- [in  std_ulogic]
          ADDRB       => addrb_i,       -- [in  std_logic_vector (14 downto 0)]
          ENB         => ENB,           -- [in  std_ulogic]
          WEB         => web_i,         -- [in  std_logic_vector (3 downto 0)]
          DIB         => data_inb_i,    -- [in  std_logic_vector (31 downto 0)]
          DIPB        => data_inpb_i,   -- [in  std_logic_vector (3 downto 0)]
          DOB         => data_outb_i,   -- [out std_logic_vector (31 downto 0)]
          DOPB        => data_outpb_i,  -- [out std_logic_vector (3 downto 0)]
          SSRB        => '0',           -- [in  std_ulogic]
          REGCEB      => '1',           -- [in  std_ulogic]
          CASCADEOUTB => open,          -- [out std_ulogic]
          CASCADEINB  => '0'            -- [in  std_ulogic]
          );                            -- [in std_logic_vector (3 downto 0)]
    end generate Using_S36_Virtex4;

    Using_S36_Spartan3A : if (C_TARGET = SPARTAN3A)    or
                             (C_TARGET = SPARTAN3AN)   or
                             (C_TARGET = SPARTAN3Adsp) generate
      signal wea_i   : std_logic_vector(0 to 3);
      signal web_i   : std_logic_vector(0 to 3);
      signal addra_i : std_logic_vector(13 downto 0);
      signal addrb_i : std_logic_vector(13 downto 0);
    begin

      Pad_RAMB16_Signals : process (ADDRA, ADDRB, WEA, WEB) is
      begin  -- process Pad_RAMB16_Signals
        wea_i                              <= (others => '0');
        wea_i(WEA'range)                   <= WEA;
        addra_i                            <= (others => '0');
        addra_i(13 downto 14-C_ADDR_WIDTH) <= ADDRA;
        web_i                              <= (others => '0');
        web_i(WEB'range)                   <= WEB;
        addrb_i                            <= (others => '0');
        addrb_i(13 downto 14-C_ADDR_WIDTH) <= ADDRB;
      end process Pad_RAMB16_Signals;

      RAMB16BWE_I1 : RAMB16BWE
        generic map (
          DATA_WIDTH_A        => 36,    -- [integer]
          DATA_WIDTH_B        => 36,    -- [integer]
          SIM_COLLISION_CHECK => sim_check_mode,
          WRITE_MODE_A        => write_mode,
          WRITE_MODE_B        => write_mode
          )                             -- [integer]
        port map (
                                        -- Port A
          CLKA  => CLKA,                -- [in  std_ulogic]
          ADDRA => addra_i,             -- [in  std_logic_vector (13 downto 0)]
          ENA   => ENA,                 -- [in  std_ulogic]
          WEA   => wea_i,               -- [in  std_logic_vector (3 downto 0)]
          DIA   => data_ina_i,          -- [in  std_logic_vector (31 downto 0)]
          DIPA  => data_inpa_i,         -- [in  std_logic_vector (3 downto 0)]
          DOA   => data_outa_i,         -- [out std_logic_vector (31 downto 0)]
          DOPA  => data_outpa_i,        -- [out std_logic_vector (3 downto 0)]
          SSRA  => '0',                 -- [in  std_ulogic]

                                        -- Port B
          CLKB  => CLKB,                -- [in  std_ulogic]
          ADDRB => addrb_i,             -- [in  std_logic_vector (13 downto 0)]
          ENB   => ENB,                 -- [in  std_ulogic]
          WEB   => web_i,               -- [in  std_logic_vector (3 downto 0)]
          DIB   => data_inb_i,          -- [in  std_logic_vector (31 downto 0)]
          DIPB  => data_inpb_i,         -- [in  std_logic_vector (3 downto 0)]
          DOB   => data_outb_i,         -- [out std_logic_vector (31 downto 0)]
          DOPB  => data_outpb_i,        -- [out std_logic_vector (3 downto 0)]
          SSRB  => '0'                  -- [in  std_ulogic]
          );                            -- [in std_logic_vector (3 downto 0)]
    end generate Using_S36_Spartan3A;


    Not_Using_Byte_Enable_BRAM36 : if (not byte_enable_bram_arch) generate
      -- Write enables is tied one for each bram block
      The_BRAMs : for I in 0 to nr_of_brams-1 generate
        RAMB16_S36_S36_1 : RAMB16_S36_S36
          generic map (
            SIM_COLLISION_CHECK => sim_check_mode,
            WRITE_MODE_A        => write_mode,
            WRITE_MODE_B        => write_mode
            )
          port map (
                                        -- Port A
            CLKA  => CLKA,              -- [in  std_ulogic]
            ENA   => ENA,               -- [in  std_ulogic]
            WEA   => WEA(I),            -- [in  std_ulogic]
            DIA   => data_ina_i(I*32 to I*32+31),  -- [in  std_logic_vector (31 downto 0)]
            DIPA  => data_inpa_i(I*4 to I*4+3),  -- [in  std_logic_vector (3 downto 0)]
            ADDRA => addra_i,           -- [in  std_logic_vector ( 8 downto 0)]
            DOA   => data_outa_i(I*32 to I*32+31),  -- [out std_logic_vector (31 downto 0)]
            DOPA  => data_outpa_i(I*4 to I*4+3),  -- [out std_logic_vector ( 3 downto 0)]
            SSRA  => '0',               -- [in  std_ulogic]
                                        -- Port B
            CLKB  => CLKB,              -- [in  std_ulogic]
            ENB   => ENB,               -- [in  std_ulogic]
            WEB   => WEB(I),            -- [in  std_ulogic]
            DIB   => data_inb_i(I*32 to I*32+31),  -- [in  std_logic_vector (31 downto 0)]
            DIPB  => data_inpb_i(I*4 to I*4+3),  -- [in  std_logic_vector (3 downto 0)]
            ADDRB => addrb_i,           -- [in  std_logic_vector ( 8 downto 0)]
            DOB   => data_outb_i(I*32 to I*32+31),  -- [out std_logic_vector (31 downto 0)]
            DOPB  => data_outpb_i(I*4 to I*4+3),  -- [out std_logic_vector ( 3 downto 0)]
            SSRB  => '0'                -- [in  std_ulogic]
            );
      end generate The_BRAMs;
    end generate Not_Using_Byte_Enable_BRAM36;
  end generate Using_B16_S36;


  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  --  BRAM organizaed as x18
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------

  Using_B16_S18 : if (What_BRAM.What_Kind = B16_S18) or (What_BRAM.What_Kind = B36_S18) generate

    Using_S36_Virtex5 : if (C_TARGET = VIRTEX5) generate
      signal wea_i   : std_logic_vector(0 to 3);
      signal web_i   : std_logic_vector(0 to 3);
      signal addra_i : std_logic_vector(15 downto 0);
      signal addrb_i : std_logic_vector(15 downto 0);
    begin

      Pad_RAMB16_Signals : process (ADDRA, ADDRB, WEA, WEB) is
      begin  -- process Pad_RAMB16_Signals
        wea_i                              <= (others => '0');
        wea_i(WEA'range)                   <= WEA;
        addra_i                            <= (others => '0');
                                        -- Address bit 15 is only used when BRAM are cascaded
        addra_i(14 downto 15-C_ADDR_WIDTH) <= ADDRA;
        web_i                              <= (others => '0');
        web_i(WEB'range)                   <= WEB;
        addrb_i                            <= (others => '0');
                                        -- Address bit 15 is only used when BRAM are cascaded
        addrb_i(14 downto 15-C_ADDR_WIDTH) <= ADDRB;
      end process Pad_RAMB16_Signals;

      The_BRAMs : for I in 0 to nr_of_brams-1 generate
        signal wea_ii : std_logic_vector(0 to 3);
        signal dia_i  : std_logic_vector(0 to 31);
        signal diap_i : std_logic_vector(0 to 3);
        signal doa_i  : std_logic_vector(0 to 31);
        signal doap_i : std_logic_vector(0 to 3);
        signal web_ii : std_logic_vector(0 to 3);
        signal dib_i  : std_logic_vector(0 to 31);
        signal dibp_i : std_logic_vector(0 to 3);
        signal dob_i  : std_logic_vector(0 to 31);
        signal dobp_i : std_logic_vector(0 to 3);
      begin

        wea_ii                       <= wea_i(I*2 to I*2+1) & wea_i(I*2 to I*2+1);
        dia_i                        <= "0000000000000000" & data_ina_i(I*16 to I*16+15);
        diap_i                       <= "00" & data_inpa_i(I*2 to I*2+1);
        data_outa_i(I*16 to I*16+15) <= doa_i(16 to 31);
        data_outpa_i(I*2 to I*2+1)   <= doap_i(2 to 3);
        web_ii                       <= web_i(I*2 to I*2+1) & web_i(I*2 to I*2+1);
        dib_i                        <= "0000000000000000" & data_inb_i(I*16 to I*16+15);
        dibp_i                       <= "00" & data_inpb_i(I*2 to I*2+1);
        data_outb_i(I*16 to I*16+15) <= dob_i(16 to 31);
        data_outpb_i(I*2 to I*2+1)   <= dobp_i(2 to 3);

        RAMB36_I1 : RAMB36
          generic map (
            DOA_REG             => 0,               -- [integer]
            DOB_REG             => 0,               -- [integer]
            RAM_EXTENSION_A     => "NONE",          -- [string]
            RAM_EXTENSION_B     => "NONE",          -- [string]
            READ_WIDTH_A        => 18,              -- [integer]
            READ_WIDTH_B        => 18,              -- [integer]
            SIM_COLLISION_CHECK => sim_check_mode,  -- [string]
            WRITE_MODE_A        => write_mode,      -- [string]
            WRITE_MODE_B        => write_mode,      -- [string]
            WRITE_WIDTH_A       => 18,              -- [integer]
            WRITE_WIDTH_B       => 18)              -- [integer]
          port map (
            CLKA => CLKA,                           -- [in              
            ENA  => ENA,                            -- [in  std_ulogic]

            ADDRA          => addra_i,  -- [in  std_logic_vector(15 downto 0)]
            WEA            => wea_ii,   -- [in  std_logic_vector(3 downto 0)]
            DIA            => dia_i,    -- [in  std_logic_vector (31 downto 0)]
            DIPA           => diap_i,   -- [in  std_logic_vector (3 downto 0)]
            DOA            => doa_i,    -- [out std_logic_vector (31 downto 0)]
            DOPA           => doap_i,   -- [out std_logic_vector (3 downto 0)]
            SSRA           => '0',      -- [in  std_ulogic]
            REGCEA         => '1',      -- [in  std_ulogic]
            CASCADEOUTLATA => open,     -- [out std_ulogic]
            CASCADEINLATA  => '0',      -- [in  std_ulogic]
            CASCADEINREGA  => '0',      -- [in  std_ulogic]
            CASCADEOUTREGA => open,     -- [out std_ulogic]

            CLKB => CLKB,               -- [in  std_ulogic]            
            ENB  => ENB,                -- [in  std_ulogic]

            ADDRB          => addrb_i,  -- [in  std_logic_vector(15 downto 0)]
            WEB            => web_ii,   -- [in std_logic_vector(3 downto 0)]
            DIB            => dib_i,    -- [in  std_logic_vector (31 downto 0)]
            DIPB           => dibp_i,   -- [in  std_logic_vector (3 downto 0)]
            DOB            => dob_i,    -- [out std_logic_vector (31 downto 0)]
            DOPB           => dobp_i,   -- [out std_logic_vector (3 downto 0)]
            SSRB           => '0',      -- [in  std_ulogic]
            REGCEB         => '1',      -- [in  std_ulogic]
            CASCADEOUTLATB => open,     -- [out std_ulogic]
            CASCADEINLATB  => '0',      -- [in  std_ulogic]
            CASCADEINREGB  => '0',      -- [in  std_ulogic]
            CASCADEOUTREGB => open);    -- [out std_ulogic]