ram_module.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

  constant byte_enable_bram_arch : boolean := (C_TARGET = VIRTEX5)   or (C_TARGET = VIRTEX4)    or
                                              (C_TARGET = SPARTAN3A) or (C_TARGET = SPARTAN3AN) or
                                              (C_TARGET = SPARTAN3Adsp);
  constant arch_36kbit_bram      : boolean := (C_TARGET = VIRTEX5);

  constant write_mode     : string := "READ_FIRST";
  constant sim_check_mode : string := "NONE";

  type bram_kind is (DISTRAM, B16_S1, B16_S2, B16_S4, B16_S9, B16_S18, B16_S36, B36_S1, B36_S2, B36_S4, B36_S9, B36_S18, B36_S36);

  type BRAM_TYPE is record
    What_Kind   : bram_kind;
    Data_size   : natural;
    Addr_size   : natural;
    Parity_size : natural;
    Par_Padding : natural;
  end record BRAM_TYPE;

  type ramb36_index_vector_type is array (boolean) of natural;
  constant ramb36_index_vector : ramb36_index_vector_type := (false => 0, true => 6);
  constant is_ram36            : natural                  := ramb36_index_vector(arch_36kbit_bram);

  type ram_addr_vector is array (natural range 1 to 14) of integer;
  type ram_select_vector is array (boolean) of ram_addr_vector;
  constant ram_select_lookup : ram_select_vector :=
    (false => (1, 2, 3, 4, 5, 6, 7, 8, 9+is_ram36, 10+is_ram36, 11+is_ram36, 12+is_ram36, 13+is_ram36, 14+is_ram36),
     true  => (9+is_ram36, 9+is_ram36, 9+is_ram36, 9+is_ram36, 9+is_ram36, 9+is_ram36,
               9+is_ram36, 9+is_ram36, 9+is_ram36, 10+is_ram36, 11+is_ram36, 12+is_ram36, 13+is_ram36, 14+is_ram36));

  type bram_type_vector is array (natural range 1 to 21) of BRAM_TYPE;
  constant bram_type_lookup : bram_type_vector :=
    (1  => (what_kind => DISTRAM, Data_size => 8, Addr_size => 1, Parity_size => 0, Par_Padding => 0),
     2  => (what_kind => DISTRAM, Data_size => 8, Addr_size => 2, Parity_size => 0, Par_Padding => 0),
     3  => (what_kind => DISTRAM, Data_size => 8, Addr_size => 3, Parity_size => 0, Par_Padding => 0),
     4  => (what_kind => DISTRAM, Data_size => 8, Addr_size => 4, Parity_size => 0, Par_Padding => 0),
     5  => (what_kind => DISTRAM, Data_size => 8, Addr_size => 5, Parity_size => 0, Par_Padding => 0),
     6  => (what_kind => DISTRAM, Data_size => 8, Addr_size => 6, Parity_size => 0, Par_Padding => 0),
     7  => (what_kind => DISTRAM, Data_size => 8, Addr_size => 7, Parity_size => 0, Par_Padding => 0),
     8  => (what_kind => DISTRAM, Data_size => 8, Addr_size => 8, Parity_size => 0, Par_Padding => 0),

     9  => (what_kind => B16_S36, Data_size => 32, Addr_size => 9, Parity_size => 4, Par_Padding => 0),
     10 => (what_kind => B16_S18, Data_size => 16, Addr_size => 10, Parity_size => 2, Par_Padding => 0),
     11 => (what_kind => B16_S9,  Data_size => 8, Addr_size => 11, Parity_size => 1, Par_Padding => 0),
     12 => (what_kind => B16_S4,  Data_size => 4, Addr_size => 12, Parity_size => 0, Par_Padding => 1),
     13 => (what_kind => B16_S2,  Data_size => 2, Addr_size => 13, Parity_size => 0, Par_Padding => 1),
     14 => (what_kind => B16_S1,  Data_size => 1, Addr_size => 14, Parity_size => 0, Par_Padding => 1),
     
     15 => (what_kind => B36_S36, Data_size => 32, Addr_size => 10, Parity_size => 4, Par_Padding => 0),
     16 => (what_kind => B36_S36, Data_size => 32, Addr_size => 10, Parity_size => 4, Par_Padding => 0),
     17 => (what_kind => B36_S18, Data_size => 16, Addr_size => 11, Parity_size => 2, Par_Padding => 0),
     18 => (what_kind => B36_S9,  Data_size => 8, Addr_size => 12, Parity_size => 1, Par_Padding => 0),
     19 => (what_kind => B36_S4,  Data_size => 4, Addr_size => 13, Parity_size => 0, Par_Padding => 1),
     20 => (what_kind => B36_S2,  Data_size => 2, Addr_size => 14, Parity_size => 0, Par_Padding => 1),
     21 => (what_kind => B36_S1,  Data_size => 1, Addr_size => 15, Parity_size => 0, Par_Padding => 1)
     );

  constant What_BRAM : BRAM_TYPE := bram_type_lookup(ram_select_lookup(C_FORCE_BRAM)(C_ADDR_WIDTH));

  constant bram_full_data_width : natural := What_BRAM.Data_size + What_BRAM.Parity_size;

  constant nr_of_brams         : natural := (C_DATA_WIDTH + bram_full_data_width-1)/bram_full_data_width;
  constant just_data_bits_size : natural := nr_of_brams*What_BRAM.Data_size;

  constant Using_Parity_bits : boolean := C_DATA_WIDTH > just_data_bits_size;

  -- local signals for padding if the size doesn't match perfectly
  signal addra_i     : std_logic_vector(0 to What_BRAM.Addr_size-1);
  signal addrb_i     : std_logic_vector(0 to What_BRAM.Addr_size-1);
  signal data_ina_i  : std_logic_vector(0 to nr_of_brams*What_BRAM.Data_size-1);
  signal data_inb_i  : std_logic_vector(0 to nr_of_brams*What_BRAM.Data_size-1);
  signal data_outa_i : std_logic_vector(0 to nr_of_brams*What_BRAM.Data_size-1);
  signal data_outb_i : std_logic_vector(0 to nr_of_brams*What_BRAM.Data_size-1);

  signal data_inpa_i  : std_logic_vector(0 to nr_of_brams*What_BRAM.Parity_size-1+What_BRAM.Par_Padding);
  signal data_inpb_i  : std_logic_vector(0 to nr_of_brams*What_BRAM.Parity_size-1+What_BRAM.Par_Padding);
  signal data_outpa_i : std_logic_vector(0 to nr_of_brams*What_BRAM.Parity_size-1+What_BRAM.Par_Padding);
  signal data_outpb_i : std_logic_vector(0 to nr_of_brams*What_BRAM.Parity_size-1+What_BRAM.Par_Padding);

begin  -- architecture IMP
  
  Data_Size_Less_Than_Bram_Size: if (C_DATA_WIDTH < just_data_bits_size) generate
    padding_vectors : process(ADDRA, ADDRB, DATA_INA, DATA_INB, data_outa_i,
                              data_outb_i, data_outpa_i, data_outpb_i) is
    begin  -- process padding_vectors
      addra_i              <= (others => '0');
      addra_i(ADDRA'range) <= ADDRA;
      addrb_i              <= (others => '0');
      addrb_i(ADDRB'range) <= ADDRB;

      -- Default drive the parity inputs to '0'
      data_inpa_i <= (others => '0');
      data_inpb_i <= (others => '0');
      
      data_ina_i                 <= (others => '0');
      data_ina_i(DATA_INA'range) <= DATA_INA;
      DATA_OUTA                  <= data_outa_i(DATA_OUTA'range);
      data_inb_i                 <= (others => '0');
      data_inb_i(DATA_INB'range) <= DATA_INB;
      DATA_OUTB                  <= data_outb_i(DATA_OUTB'range);
    end process padding_vectors;    
  end generate Data_Size_Less_Than_Bram_Size;

  Data_Size_Larger_Than_BRAM_Size: if (C_DATA_WIDTH > just_data_bits_size) generate
    padding_vectors : process(ADDRA, ADDRB, DATA_INA, DATA_INB, data_outa_i,
                              data_outb_i, data_outpa_i, data_outpb_i) is
    begin  -- process padding_vectors
      addra_i              <= (others => '0');
      addra_i(ADDRA'range) <= ADDRA;
      addrb_i              <= (others => '0');
      addrb_i(ADDRB'range) <= ADDRB;

      -- Default drive the parity inputs to '0'
      data_inpa_i <= (others => '0');
      data_inpb_i <= (others => '0');

      data_ina_i                                           <= DATA_INA(0 to just_data_bits_size-1);
      data_inpa_i(0 to C_DATA_WIDTH-just_data_bits_size-1) <= DATA_INA(just_data_bits_size to C_DATA_WIDTH-1);
      DATA_OUTA                                            <= data_outa_i & data_outpa_i(0 to C_DATA_WIDTH-just_data_bits_size-1);
      data_inb_i                                           <= DATA_INB(0 to just_data_bits_size-1);
      data_inpb_i(0 to C_DATA_WIDTH-just_data_bits_size-1) <= DATA_INB(just_data_bits_size to C_DATA_WIDTH-1);
      DATA_OUTB                                            <= data_outb_i & data_outpb_i(0 to C_DATA_WIDTH-just_data_bits_size-1);
    end process padding_vectors;    
  end generate Data_Size_Larger_Than_BRAM_Size;

  Data_Size_Equal_To_BRAM_Size: if (C_DATA_WIDTH = just_data_bits_size) generate
    padding_vectors : process(ADDRA, ADDRB, DATA_INA, DATA_INB, data_outa_i,
                              data_outb_i, data_outpa_i, data_outpb_i) is
    begin  -- process padding_vectors
      addra_i              <= (others => '0');
      addra_i(ADDRA'range) <= ADDRA;
      addrb_i              <= (others => '0');
      addrb_i(ADDRB'range) <= ADDRB;

      -- Default drive the parity inputs to '0'
      data_inpa_i <= (others => '0');
      data_inpb_i <= (others => '0');

      data_ina_i <= DATA_INA;
      DATA_OUTA  <= data_outa_i;
      data_inb_i <= DATA_INB;
      DATA_OUTB  <= data_outb_i;
    end process padding_vectors;    
  end generate Data_Size_Equal_To_BRAM_Size;

  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  --  BRAM organizaed as x36
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------

  Using_B16_S36 : if (What_BRAM.What_Kind = B16_S36) or (What_BRAM.What_Kind = B36_S36) generate
    Using_S36_Virtex5 : if (C_TARGET = VIRTEX5) generate
      signal wea_i   : std_logic_vector(0 to 3);
      signal web_i   : std_logic_vector(0 to 3);
      signal addra_i : std_logic_vector(15 downto 0);
      signal addrb_i : std_logic_vector(15 downto 0);
    begin

      Pad_RAMB16_Signals : process (ADDRA, ADDRB, WEA, WEB) is
      begin  -- process Pad_RAMB16_Signals
        wea_i                              <= (others => '0');
        wea_i(WEA'range)                   <= WEA;
        addra_i                            <= (others => '0');
                                        -- Address bit 15 is only used when BRAM are cascaded
        addra_i(14 downto 15-C_ADDR_WIDTH) <= ADDRA;
        web_i                              <= (others => '0');
        web_i(WEB'range)                   <= WEB;
        addrb_i                            <= (others => '0');
                                        -- Address bit 15 is only used when BRAM are cascaded
        addrb_i(14 downto 15-C_ADDR_WIDTH) <= ADDRB;
      end process Pad_RAMB16_Signals;

      RAMB36_I1 : RAMB36
        generic map (
          DOA_REG             => 0,               -- [integer]
          DOB_REG             => 0,               -- [integer]
          RAM_EXTENSION_A     => "NONE",          -- [string]
          RAM_EXTENSION_B     => "NONE",          -- [string]
          READ_WIDTH_A        => 36,              -- [integer]
          READ_WIDTH_B        => 36,              -- [integer]
          SIM_COLLISION_CHECK => sim_check_mode,  -- [string]
          WRITE_MODE_A        => write_mode,      -- [string]
          WRITE_MODE_B        => write_mode,      -- [string]
          WRITE_WIDTH_A       => 36,              -- [integer]
          WRITE_WIDTH_B       => 36)              -- [integer]
        port map (
          CLKA => CLKA,                           -- [in              
          ENA  => ENA,                            -- [in  std_ulogic]

          ADDRA          => addra_i,    -- [in  std_logic_vector(15 downto 0)]
          WEA            => wea_i,      -- [in  std_logic_vector(3 downto 0)]
          DIA            => data_ina_i,  -- [in  std_logic_vector (31 downto 0)]
          DIPA           => data_inpa_i,  -- [in  std_logic_vector (3 downto 0)]
          DOA            => data_outa_i,  -- [out std_logic_vector (31 downto 0)]
          DOPA           => data_outpa_i,  -- [out std_logic_vector (3 downto 0)]
          SSRA           => '0',        -- [in  std_ulogic]
          REGCEA         => '1',        -- [in  std_ulogic]
          CASCADEOUTLATA => open,       -- [out std_ulogic]
          CASCADEINLATA  => '0',        -- [in  std_ulogic]
          CASCADEINREGA  => '0',        -- [in  std_ulogic]
          CASCADEOUTREGA => open,       -- [out std_ulogic]

          CLKB => CLKB,                 -- [in  std_ulogic]            
          ENB  => ENB,                  -- [in  std_ulogic]

          ADDRB          => addrb_i,    -- [in  std_logic_vector(15 downto 0)]
          WEB            => web_i,      -- [in std_logic_vector(3 downto 0)]
          DIB            => data_inb_i,  -- [in  std_logic_vector (31 downto 0)]
          DIPB           => data_inpb_i,  -- [in  std_logic_vector (3 downto 0)]
          DOB            => data_outb_i,  -- [out std_logic_vector (31 downto 0)]
          DOPB           => data_outpb_i,  -- [out std_logic_vector (3 downto 0)]
          SSRB           => '0',        -- [in  std_ulogic]
          REGCEB         => '1',        -- [in  std_ulogic]
          CASCADEOUTLATB => open,       -- [out std_ulogic]
          CASCADEINLATB  => '0',        -- [in  std_ulogic]
          CASCADEINREGB  => '0',        -- [in  std_ulogic]
          CASCADEOUTREGB => open);      -- [out std_ulogic]
    end generate Using_S36_Virtex5;

    Using_S36_Virtex4 : if (C_TARGET = VIRTEX4) generate
      signal wea_i   : std_logic_vector(0 to 3);
      signal web_i   : std_logic_vector(0 to 3);
      signal addra_i : std_logic_vector(14 downto 0);
      signal addrb_i : std_logic_vector(14 downto 0);
    begin

      Pad_RAMB16_Signals : process (ADDRA, ADDRB, WEA, WEB) is
      begin  -- process Pad_RAMB16_Signals
        wea_i                              <= (others => '0');
        wea_i(WEA'range)                   <= WEA;
        addra_i                            <= (others => '0');
                                        -- Address bit 14 is only used when BRAM are cascaded
        addra_i(13 downto 14-C_ADDR_WIDTH) <= ADDRA;
        web_i                              <= (others => '0');
        web_i(WEB'range)                   <= WEB;