microblaze_isa_be_pkg.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

  subtype FPU_MANT_TYPE is std_logic_vector(IEEE754_SINGLE_MANT_POS);

  -- Number of bits to express the position in the mantissa
  subtype FPU_MANT_BIT_POS is natural range 0 to 4;
  subtype FPU_EXP_LS_TYPE is std_logic_vector(FPU_MANT_BIT_POS);

  -- Extra bits that are added to the mantissa
  constant FPU_MANT_IMPL_POS   : natural := 8;
  constant FPU_MANT_GUARD_POS  : natural := 32;
  constant FPU_MANT_ROUND_POS  : natural := 33;
  constant FPU_MANT_STICKY_POS : natural := 34;

  constant FPU_MANT_ZERO : FPU_MANT_TYPE := "00000000000000000000000";
  constant FPU_MANT_ONES : FPU_MANT_TYPE := "11111111111111111111111";

  -- Mantissa with implicit bit
  subtype FPU_MANT_I_TYPE is std_logic_vector(FPU_MANT_TYPE'left-1 to FPU_MANT_TYPE'right);

  -- Mantissa with implicit, guard, rounding, and sticky bits
  subtype FPU_MANT_IGRS_TYPE is std_logic_vector(FPU_MANT_TYPE'left-1 to FPU_MANT_TYPE'right+3);

  -- Processor Version Register
  subtype PVR_TYPE is DATA_TYPE;

  -- Where in the IMM_WORD_TYPE the sign bit is located
  constant IMM_SIGN_BIT_LOC : natural := 0;
  -- Where in a DATA_WORD_TYPE the IMM_REG bits shall go
  subtype  IMM_REG_POS_TYPE is natural range 0 to 15;

  -- Where the Byte and DOUBLET sign bit are positioned in a QUADLET;
  constant BYTE_SIGN_POS    : natural := 24;
  constant DOUBLET_SIGN_POS : natural := 16;
  constant QUADLET_SIGN_POS : natural := 0;

  -- Position with a DATA_WORD where byte/doublets are located

  -- Position where the sign bit shall go for byte sign extension
  subtype SIGNEXT_BYTE_POS_TYPE is natural range 0 to 23;

  -- Type for handle data mirroring/steering, low_addr_bits and byte_enable
  -- Byte are numbered LSB, LSB_1, LSB_2 and MSB
  -- Where LSB are the least significant byte within a word and
  -- MSB is the most significant byte within a word
  -- Doublet are numbered in the same way
  subtype BYTE_LSB_POS_TYPE is natural range 24 to 31;
  subtype BYTE_LSB_1_POS_TYPE is natural range 16 to 23;
  subtype BYTE_LSB_2_POS_TYPE is natural range 8 to 15;
  subtype BYTE_MSB_POS_TYPE is natural range 0 to 7;
  subtype DOUBLET_LSB_POS_TYPE is natural range 16 to 31;
  subtype DOUBLET_MSB_POS_TYPE is natural range 0 to 15;

  subtype  LOW_ADDR_POS_TYPE is natural range 30 to 31;
  subtype  LOW_ADDR_TYPE is std_logic_vector(0 to 1);
  subtype  BYTE_ENABLE_TYPE is std_logic_vector(0 to 3);
  constant BYTE_0             : LOW_ADDR_TYPE := "00";
  constant BYTE_1             : LOW_ADDR_TYPE := "01";
  constant BYTE_2             : LOW_ADDR_TYPE := "10";
  constant BYTE_3             : LOW_ADDR_TYPE := "11";
  constant BYTE_ENABLE_BYTE_0 : natural       := 3;
  constant BYTE_ENABLE_BYTE_1 : natural       := 2;
  constant BYTE_ENABLE_BYTE_2 : natural       := 1;
  constant BYTE_ENABLE_BYTE_3 : natural       := 0;
  subtype  BYTE_ENABLE_DOUBLET_HIGH_TYPE is natural range 0 to 1;
  subtype  BYTE_ENABLE_DOUBLET_LOW_TYPE is natural range 2 to 3;

  -----------------------------------------------------------------------------
  -- Instruction decoding 
  -----------------------------------------------------------------------------

  -- Where in the Word the opcode is located
  subtype OPCODE_POS_TYPE is natural range 0 to 5;
  subtype OPCODE_TYPE is std_logic_vector(OPCODE_POS_TYPE);

  -- Bit location if the instruction is an immediate instruction
  constant IMMEDIATE_POS : natural   := 2;
  constant IMMEDIATE_DEC : std_logic := '1';

  -- Bit locations for Register address within the instruction
  subtype WRITE_ADDR_POS_TYPE is natural range 6 to 10;
  subtype REG1_ADDR_POS_TYPE is natural range 11 to 15;
  subtype REG2_ADDR_POS_TYPE is natural range 16 to 20;

  -- Special registers
  -- Register 0, always 0
  constant NULL_REG_ADDR : std_logic_vector(0 to 4) := "00000";
  -- Exception Register 17
  constant EXC_REG_ADDR  : std_logic_vector(0 to 4) := "10001";
  -- Break     Register 16
  constant BRK_REG_ADDR  : std_logic_vector(0 to 4) := "10000";
  -- Interrupt Register 14
  constant INT_REG_ADDR  : std_logic_vector(0 to 4) := "01110";

  -- Bit location for Result Select bit
  subtype  RESULT_SEL_POS_TYPE is natural range 0 to 1;
  constant ARITH_INSTR_DEC : std_logic_vector(0 to 1) := "00";
  constant MULTI_INSTR_DEC : std_logic_vector(0 to 1) := "01";
  constant SHIFT_INSTR_DEC : std_logic_vector(0 to 1) := "10";
  constant LOAD_STORE_DEC  : std_logic_vector(0 to 1) := "11";

  -- Additional decoding for divider/FPU
  -- Actually need bits 2 to 5 to decode properly, but the opcode
  -- that conflicts at bit 2 is currently free
  subtype  DIVFPU_POS_TYPE is natural range 3 to 5;
  constant DIVFPU_DIV_DEC : std_logic_vector(3 to 5) := "010";
  constant DIVFPU_FPU_DEC : std_logic_vector(3 to 5) := "110";

  constant DIV_UNSIGNED_POS : natural := 30;
  constant DIV_UNSIGNED_DEC : std_logic := '1';
  constant DIV_SIGNED_DEC   : std_logic := '0';
  
  
  -- Bit location for the immediate
  subtype IMMEDIATE_VALUE_POS_TYPE is natural range 16 to 31;

  -- Arithmetic opcodes
  constant ADD_DEC     : OPCODE_TYPE := "000000";
  constant RSUB_DEC    : OPCODE_TYPE := "000001";
  constant ADDC_DEC    : OPCODE_TYPE := "000010";
  constant RSUBC_DEC   : OPCODE_TYPE := "000011";
  constant ADDK_DEC    : OPCODE_TYPE := "000100";
  constant RSUBK_DEC   : OPCODE_TYPE := "000101";
  constant ADDKC_DEC   : OPCODE_TYPE := "000110";
  constant RSUBKC_DEC  : OPCODE_TYPE := "000111";
  constant ADDI_DEC    : OPCODE_TYPE := "001000";
  constant RSUBI_DEC   : OPCODE_TYPE := "001001";
  constant ADDIC_DEC   : OPCODE_TYPE := "001010";
  constant RSUBIC_DEC  : OPCODE_TYPE := "001011";
  constant ADDIK_DEC   : OPCODE_TYPE := "001100";
  constant RSUBIK_DEC  : OPCODE_TYPE := "001101";
  constant ADDIKC_DEC  : OPCODE_TYPE := "001110";
  constant RSUBIKC_DEC : OPCODE_TYPE := "001111";

  constant CARRY_UPDATE_POS : natural   := 3;
  constant KEEP_CARRY       : std_logic := '1';
  constant UPDATE_CARRY     : std_logic := '0';
  constant USE_CARRY_POS    : natural   := 4;
  constant USE_CARRY_DEC    : std_logic := '1';
  constant ADDSUB_POS       : natural   := 5;
  constant ADD_OP_DEC       : std_logic := '0';
  constant SUB_OP_DEC       : std_logic := '1';

  -- Mul opcodes
  constant MUL_DEC  : OPCODE_TYPE := "010000";
  constant MULI_DEC : OPCODE_TYPE := "011000";

  -- Barrel opcodes
  constant BS_DEC  : OPCODE_TYPE := "010001";
  constant BSI_DEC : OPCODE_TYPE := "011001";

  -- Logic opcodes
  constant OR_DEC    : OPCODE_TYPE := "100000";
  constant AND_DEC   : OPCODE_TYPE := "100001";
  constant XOR_DEC   : OPCODE_TYPE := "100010";
  constant ANDN_DEC  : OPCODE_TYPE := "100011";
  constant ORI_DEC   : OPCODE_TYPE := "101000";
  constant ANDI_DEC  : OPCODE_TYPE := "101001";
  constant XORI_DEC  : OPCODE_TYPE := "101010";
  constant ANDNI_DEC : OPCODE_TYPE := "101011";

  subtype  LOGIC_OP_POS_TYPE is natural range 4 to 5;
  constant LOGIC_OR_DEC   : LOGIC_OP_TYPE := "00";
  constant LOGIC_AND_DEC  : LOGIC_OP_TYPE := "01";
  constant LOGIC_XOR_DEC  : LOGIC_OP_TYPE := "10";
  constant LOGIC_ANDN_DEC : LOGIC_OP_TYPE := "11";

  constant SELECT_LOGIC_POS : natural   := 3;
  constant SELECT_LOGIC_DEC : std_logic := '0';
  constant SELECT_SHIFT_DEC : std_logic := '1';

  constant UNSIGNED_POS : natural   := 30;
  constant UNSIGNED_DEC : std_logic := '1';
  constant SIGNED_DEC   : std_logic := '0';

  constant COMPARE_POS     : natural   := 31;
  constant COMPARE_DEC     : std_logic := '1';
  constant NOT_COMPARE_DEC : std_logic := '0';

  subtype  ALU_OPER_POS_TYPE is natural range 0 to 2;
  constant ALU_SHIFT_SEL_POS : natural                  := 0;  -- selection between ALU and
                                        -- SHIFT_LOGIC unit in EX stage
  constant ALU_SEL           : std_logic                := '0';
  constant SHIFT_SEL         : std_logic                := '1';
  constant ALU_NOIMM_DEC     : std_logic_vector(0 to 2) := "000";

  constant ALU_OP_OP1   : std_logic_vector(0 to 1) := "00";
  constant ALU_OP_OP2   : std_logic_vector(0 to 1) := "01";
  constant ALU_OP_PLUS  : std_logic_vector(0 to 1) := "10";
  constant ALU_OP_MINUS : std_logic_vector(0 to 1) := "11";

  -- Shift opcodes and bit location for different shift operations
  constant SRX_DEC  : OPCODE_TYPE              := "100100";
  subtype  SRX_POS_TYPE is natural range 25 to 26;
  constant SRA_DEC  : std_logic_vector(0 to 1) := "00";
  constant SRC_DEC  : std_logic_vector(0 to 1) := "01";
  constant SRL_DEC  : std_logic_vector(0 to 1) := "10";
  constant SEXT_DEC : std_logic_vector(0 to 1) := "11";

  constant SEXTX_POS  : natural   := 31;
  constant SEXT8_DEC  : std_logic := '0';
  constant SEXT16_DEC : std_logic := '1';

  constant SHIFT_DIFF_BXXX_POS       : natural   := 4;  -- diff between SHIFT and BXXX
                                        -- opcodes used to control
                                        -- shift_logic bypassing of Op1
                                        -- for linked branches
  constant SHIFT_DIFF_BXXX_SHIFT_DEC : std_logic := '0';  -- shift instructions
  constant SHIFT_DIFF_BXXX_BXXX_DEC  : std_logic := '1';  -- branch instructions

  constant SEXT_OP_8   : SEXT_OP_TYPE := "00";
  constant SEXT_OP_16  : SEXT_OP_TYPE := "01";
  constant SEXT_OP_OP1 : SEXT_OP_TYPE := "10";

  constant WIC_POS_TYPE : natural   := 28;
  constant WIC_DEC      : std_logic := '1';
  constant WDC_POS_TYPE : natural   := 29;
  constant WDC_DEC      : std_logic := '1';
  constant NOT_WXC_DEC  : std_logic := '0';

  -- Barrel shifter
  constant BS_SIDE_POS_TYPE  : natural   := 21;
  constant BS_SIDE_LEFT_DEC  : std_logic := '1';
  constant BS_SIDE_RIGHT_DEC : std_logic := '0';
  constant BS_TYPE_POS_TYPE  : natural   := 22;
  constant BS_TYPE_ARITH_DEC : std_logic := '1';
  constant BS_TYPE_LOGIC_DEC : std_logic := '0';

  -- Mxs opcode and bit location for MTS or MFS
  constant MXS_DEC        : OPCODE_TYPE := "100101";
  constant MXS_POS        : natural     := 17;
  constant MFS_DEC        : std_logic   := '0';
  constant PVR_POS        : natural     := 18;
  constant PVR_DEC        : std_logic   := '1';
  constant MMU_POS        : natural     := 19;
  constant MMU_DEC        : std_logic   := '1';
  constant MTS_DEC        : std_logic   := '1';
  constant SPR_POS        : natural     := 31;
  constant SPR_PC_DEC     : std_logic   := '0';
  constant SPR_MSREXT_DEC : std_logic   := '1';

  -- When C_PVR = C_PVR_FULL
  subtype PVR_SELECT_POS_TYPE is natural range 28 to 31;
  
  -- When SPR_POS = SPR_MSREXT_DEC
  subtype  EXT_SPR_POS_TYPE is natural range 28 to 30;
  subtype  EXT_SPR_TYPE is std_logic_vector(EXT_SPR_POS_TYPE);
  constant EXT_SPR_MSR_DEC : std_logic_vector := "000";
  constant EXT_SPR_EAR_DEC : std_logic_vector := "001";
  constant EXT_SPR_ESR_DEC : std_logic_vector := "010";
  constant EXT_SPR_FSR_DEC : std_logic_vector := "011";