microblaze_isa_be_pkg.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: microblaze_isa_be_pkg.vhd,v 1.2 2007/11/07 12:47:48 stefana Exp $
-------------------------------------------------------------------------------
-- MicroBlaze_ISA -  package
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2001-2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc.
-- **
-- ** Unmodified source code is guaranteed to place and route,
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        microblaze_isa_be_pkg.vhd
-- Version:         v1.00a
-- Description:     Package with types and function supporting MicroBlaze ISA
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              microblaze_isa_be_pkg.vhd
--                 -- microblaze_isa_pkg_body.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--  goran         1-22-2001      -- First version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY>_I#|<FUNC>" , "<ENTITY>_I"
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                                -- instruction fetch
--    OF                                -- operand fetch
--    EX                                -- execute
--    MEM                               -- memory
--    WB                                -- write back
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

library microblaze_v7_10_a;
use microblaze_v7_10_a.microblaze_types.all;

package MicroBlaze_ISA is
  -----------------------------------------------------------------------------
  -- MB version constant definition
  -----------------------------------------------------------------------------
  constant MB_VERSION  : std_logic_vector(0 to 7) := "00001000";  -- v7.10.a

  -----------------------------------------------------------------------------
  -- Constant definition
  -----------------------------------------------------------------------------
  constant DATA_SIZE : natural := 32;

  -- lower and upper half-word
  subtype DATA_UPPER_HW is natural range 0 to 15;
  subtype DATA_LOWER_HW is natural range 16 to 31;

  subtype UPPER_HW_TYPE is std_logic_vector(DATA_UPPER_HW);
  subtype LOWER_HW_TYPE is std_logic_vector(DATA_LOWER_HW);

  -- The value to be added for an index in a word to get to the next higher bit
  -- The value is -1 for Big Endian since 31 is lsb and 30 is the next higher
  -- bit. The value is 1 for Little Endian since 0 is lsb and 1 is the next
  -- higher bit.
  constant NEXT_MSB_BIT : integer := -1;
  constant NEXT_LSB_BIT : integer := 1;

  -- Coding of C_PVR
  constant C_PVR_NONE  : natural := 0;
  constant C_PVR_BASIC : natural := 1;
  constant C_PVR_FULL  : natural := 2;
  
  -- Coding of C_USE_MMU
  constant C_MMU_NONE     : natural := 0;
  constant C_MMU_USERMODE : natural := 1;
  constant C_MMU_PROTECT  : natural := 2;
  constant C_MMU_VIRTUAL  : natural := 3;

  -----------------------------------------------------------------------------
  -- Type definitions
  -----------------------------------------------------------------------------
  subtype INSTRUCTION_WORD_TYPE is std_logic_vector(0 to 31);
  subtype QUADLET_TYPE is std_logic_vector(0 to 31);
  subtype DOUBLET_TYPE is std_logic_vector(0 to 15);
  subtype BYTE_TYPE is std_logic_vector(0 to 7);
  subtype DATA_WORD_TYPE is QUADLET_TYPE;
  subtype DATA_WORD_PLUS1_TYPE is std_logic_vector(0 to 32);
  subtype DATA_WORD_MINUS1_TYPE is std_logic_vector(0 to 30);
  subtype ADDR_WORD_TYPE is std_logic_vector(0 to 31);

  subtype REG_ADDRESS_TYPE is std_logic_vector(0 to 4);
  subtype IMM_WORD_TYPE is std_logic_vector(0 to 15);
  subtype ALU_OP_TYPE is std_logic_vector(0 to 1);
  subtype SEXT_OP_TYPE is std_logic_vector(0 to 1);
  subtype SHIFT_OP_TYPE is std_logic_vector(0 to 1);
  subtype LOGIC_OPER_POS_TYPE is natural range 4 to 5;
  subtype LOGIC_OP_TYPE is std_logic_vector(0 to 1);
  subtype RESULT_SEL_TYPE is std_logic_vector(0 to 1);

  -- Barrel shifter
  subtype BSNUM_POS_TYPE is natural range 27 to 31;
  subtype BSNUM_TYPE is std_logic_vector(BSNUM_POS_TYPE);

  -- MSR type and bit positions
  subtype  MSR_REG_TYPE is std_logic_vector(21 to 31);  -- For area version
  subtype  MSR_REG_POS_TYPE is natural range 17 to 31;
  subtype  MSR_TYPE is std_logic_vector(MSR_REG_POS_TYPE);
  constant MSR_BE_POS  : MSR_REG_POS_TYPE := 31;
  constant MSR_IE_POS  : MSR_REG_POS_TYPE := 30;
  constant MSR_C_POS   : MSR_REG_POS_TYPE := 29;
  constant MSR_BIP_POS : MSR_REG_POS_TYPE := 28;
  constant MSR_FSL_POS : MSR_REG_POS_TYPE := 27;
  constant MSR_ICE_POS : MSR_REG_POS_TYPE := 26;
  constant MSR_DZ_POS  : MSR_REG_POS_TYPE := 25;
  constant MSR_DCE_POS : MSR_REG_POS_TYPE := 24;
  constant MSR_EE_POS  : MSR_REG_POS_TYPE := 23;
  constant MSR_EIP_POS : MSR_REG_POS_TYPE := 22;
  constant MSR_PVR_POS : MSR_REG_POS_TYPE := 21;
  constant MSR_UM_POS  : MSR_REG_POS_TYPE := 20;
  constant MSR_UMS_POS : MSR_REG_POS_TYPE := 19;
  constant MSR_VM_POS  : MSR_REG_POS_TYPE := 18;
  constant MSR_VMS_POS : MSR_REG_POS_TYPE := 17;

  -- Carry copy bit in zero extended MSR
  constant MSR_CC_POS : natural := 0;

  -- Multiplier operand
  subtype MUL_OP_POS_TYPE is natural range 0 to 17;
  subtype MUL_OP_TYPE is std_logic_vector(MUL_OP_POS_TYPE);

  -- Multiplier result
  subtype MUL_RES_POS_TYPE is natural range 0 to 35;
  subtype MUL_RES_TYPE is std_logic_vector(MUL_RES_POS_TYPE);

  -- Result lower and upper half-word
  -- Multiplier produces 36-bit result
  -- Bits 0-3 are not used for 32-bit result
  subtype MUL_RES_WORD is natural range 4 to 35;
  subtype MUL_RES_UPPER_HW is natural range 4 to 19;
  subtype MUL_RES_LOWER_HW is natural range 20 to 35;

  -- ESR and EAR type and bit positions
  subtype  BTR_TYPE is DATA_TYPE;
  subtype  EAR_TYPE is DATA_TYPE;
  subtype  EDR_TYPE is DATA_TYPE;
  subtype  ESR_REG_POS_TYPE is natural range 19 to 31;
  subtype  ESR_TYPE is std_logic_vector(ESR_REG_POS_TYPE);
  subtype  ESR_EC_POS_TYPE is natural range 27 to 31;
  subtype  ESR_EC_TYPE is std_logic_vector(ESR_EC_POS_TYPE);
  constant EC_UNALIGNED_DATA : ESR_EC_TYPE := "00001";
  constant EC_ILLEGAL_OP     : ESR_EC_TYPE := "00010";
  constant EC_IBUS_ERROR     : ESR_EC_TYPE := "00011";
  constant EC_DBUS_ERROR     : ESR_EC_TYPE := "00100";
  constant EC_DIV_BY_0       : ESR_EC_TYPE := "00101";
  constant EC_FPU            : ESR_EC_TYPE := "00110";

  -- FPU Operation type
  subtype FPU_OP_POS_TYPE is natural range 22 to 24;
  subtype FPU_OP_TYPE is std_logic_vector(FPU_OP_POS_TYPE);
  constant FPU_OP_ADD_DEC  : FPU_OP_TYPE := "000";
  constant FPU_OP_SUB_DEC  : FPU_OP_TYPE := "001";
  constant FPU_OP_MUL_DEC  : FPU_OP_TYPE := "010";
  constant FPU_OP_DIV_DEC  : FPU_OP_TYPE := "011";
  constant FPU_OP_CMP_DEC  : FPU_OP_TYPE := "100";
  constant FPU_OP_FLT_DEC  : FPU_OP_TYPE := "101";
  constant FPU_OP_INT_DEC  : FPU_OP_TYPE := "110";
  constant FPU_OP_SQRT_DEC : FPU_OP_TYPE := "111";

  -- FPU_OP positions to determine add or subtract
  constant FPU_OP_ADDSUB_POS : natural := 24;

  -- FPU Condition
  subtype  FPU_COND_POS_TYPE is natural range 25 to 27;
  subtype  FPU_COND_TYPE is std_logic_vector(FPU_COND_POS_TYPE);
  constant FPU_COND_UN_DEC : FPU_COND_TYPE := "000";
  constant FPU_COND_LT_DEC : FPU_COND_TYPE := "001";
  constant FPU_COND_EQ_DEC : FPU_COND_TYPE := "010";
  constant FPU_COND_LE_DEC : FPU_COND_TYPE := "011";
  constant FPU_COND_GT_DEC : FPU_COND_TYPE := "100";
  constant FPU_COND_NE_DEC : FPU_COND_TYPE := "101";
  constant FPU_COND_GE_DEC : FPU_COND_TYPE := "110";

  -- FPU_Cond positions to determine conditions
  constant FPU_COND_GT_POS : natural := 25;
  constant FPU_COND_EQ_POS : natural := 26;
  constant FPU_COND_LT_POS : natural := 27;

  -- FSR type and bit positions
  subtype  FSR_REG_POS_TYPE is natural range 27 to 31;
  subtype  FSR_TYPE is std_logic_vector(FSR_REG_POS_TYPE);
  constant FSR_IO : FSR_REG_POS_TYPE := 27;
  constant FSR_DZ : FSR_REG_POS_TYPE := 28;
  constant FSR_OF : FSR_REG_POS_TYPE := 29;
  constant FSR_UF : FSR_REG_POS_TYPE := 30;
  constant FSR_DO : FSR_REG_POS_TYPE := 31;

  -- IEEE 754 single-precision format
  constant IEEE754_SINGLE_SIGN_POS : natural := 0;
  subtype  IEEE754_SINGLE_EXP_POS is natural range 1 to 8;
  subtype  IEEE754_SINGLE_MANT_POS is natural range 9 to 31;

  -- MSb of the mantissa selects between quiet and signaling NaN
  constant FPU_NAN_POS   : natural   := 9;
  constant FPU_NAN_QUIET : std_logic := '1';
  constant FPU_NAN_SIG   : std_logic := '0';

  subtype FPU_EXP_TYPE is std_logic_vector(IEEE754_SINGLE_EXP_POS);

  -- All zero and all ones exponent
  constant FPU_EXP_ZERO : FPU_EXP_TYPE := "00000000";
  constant FPU_EXP_ONES : FPU_EXP_TYPE := "11111111";