wb_mux_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

  function Map_Used_Data_Bits(
    I                         : integer;
    WB_Steered_Read_Data      : in DATA_TYPE;
    WB_MEM_Result             : in DATA_TYPE;
    WB_Mul_Result             : in DATA_TYPE;
    WB_FPU_Result             : in DATA_TYPE;
    WB_MMU_Result             : in DATA_TYPE;
    WB_ESR                    : in ESR_TYPE;
    WB_EAR                    : in EAR_TYPE;
    WB_EDR                    : in EDR_TYPE;
    WB_FSR                    : in FSR_TYPE;
    WB_PVR                    : in PVR_TYPE;
    WB_BTR                    : in BTR_TYPE)
  return std_logic_vector is
    variable tmp  : std_logic_vector(0 to MAX_SOURCES - 1):= (others=>'0');
    variable idx  : natural;
  begin
    tmp(0)  := WB_Steered_Read_Data(I);
    tmp(1)  := WB_MEM_Result(I);
    idx     := 2;
    
    if C_USE_HW_MUL then
      tmp(idx):= WB_Mul_Result(I);
      idx     := idx + 1;
    end if;
    if C_USE_FPU then
      tmp(idx):= WB_FPU_Result(I);
      idx     := idx + 1;
    end if;
    if C_USE_MMU >= C_MMU_PROTECT then
      tmp(idx):= WB_MMU_Result(I);
      idx     := idx + 1;
    end if;
    if C_USE_FPU and I >= FSR_TYPE'left and I <= FSR_TYPE'right then
      tmp(idx):= WB_FSR(I);
      idx     := idx + 1;
    end if;
    if C_USE_EXCEPTIONS and I >= ESR_TYPE'left and I <= ESR_TYPE'right then
      tmp(idx):= WB_ESR(I);
      idx     := idx + 1;
    end if;
    if C_USE_EXCEPTIONS and I >= EAR_TYPE'left and I <= EAR_TYPE'right then
      tmp(idx):= WB_EAR(I);
      idx     := idx + 1;
    end if;
    if C_USE_EXCEPTIONS and I >= BTR_TYPE'left and I <= BTR_TYPE'right then
      tmp(idx):= WB_BTR(I);
      idx     := idx + 1;
    end if;
    if C_FSL_EXCEPTION and I >= EDR_TYPE'left and I <= EDR_TYPE'right then
      tmp(idx):= WB_EDR(I);
      idx     := idx + 1;
    end if;
    if C_PVR /= 0 and I >= PVR_TYPE'left and I <= PVR_TYPE'right then
      tmp(idx):= WB_PVR(I);
      idx     := idx + 1;
    end if;

    return tmp;
  end function Map_Used_Data_Bits;
  
    
  -- Map used select signals to the source vector (per bit).
  -- (If adding additional sources the Map_Used_Data_Bits, 
  --  Map_Used_Select_Bits and Count_Bus_Bits functions must be updated)
  function Map_Used_Select_Bits(
    I                         : integer;
    WB_Sel_DataBus_Read_Data  : in boolean;
    WB_Sel_MEM_Res            : in boolean;
    WB_Sel_MUL_Res            : in boolean;
    WB_Sel_FPU_Res            : in boolean;
    WB_Sel_MMU_Res            : in boolean;
    WB_Sel_SPR_ESR            : in boolean;
    WB_Sel_SPR_EAR            : in boolean;
    WB_Sel_SPR_EDR            : in boolean;
    WB_Sel_SPR_FSR            : in boolean;
    WB_Sel_SPR_PVR            : in boolean;
    WB_Sel_SPR_BTR            : in boolean)
  return std_logic_vector is
    variable tmp  : std_logic_vector(0 to MAX_SOURCES - 1):= (others=>'0');
    variable tmp2 : std_logic_vector(0 to SELECT_LAST):= (others=>'0');
    variable idx  : natural;
  begin
    tmp(0)  := b2std(WB_Sel_DataBus_Read_Data);
    tmp(1)  := b2std(WB_Sel_MEM_Res);
    idx     := 2;
    
    if C_USE_HW_MUL then
      tmp(idx):= b2std(WB_Sel_MUL_Res);
      idx     := idx + 1;
    end if;
    if C_USE_FPU then
      tmp(idx):= b2std(WB_Sel_FPU_Res);
      idx     := idx + 1;
    end if;
    if C_USE_FPU and I >= FSR_TYPE'left and I <= FSR_TYPE'right then
      tmp(idx):= b2std(WB_Sel_SPR_FSR);
      idx     := idx + 1;
    end if;
    if C_USE_MMU >= C_MMU_PROTECT then
      tmp(idx):= b2std(WB_Sel_MMU_Res);
      idx     := idx + 1;
    end if;
    if C_USE_EXCEPTIONS and I >= ESR_TYPE'left and I <= ESR_TYPE'right then
      tmp(idx):= b2std(WB_Sel_SPR_ESR);
      idx     := idx + 1;
    end if;
    if C_USE_EXCEPTIONS and I >= EAR_TYPE'left and I <= EAR_TYPE'right then
      tmp(idx):= b2std(WB_Sel_SPR_EAR);
      idx     := idx + 1;
    end if;
    if C_USE_EXCEPTIONS and I >= BTR_TYPE'left and I <= BTR_TYPE'right then
      tmp(idx):= b2std(WB_Sel_SPR_BTR);
      idx     := idx + 1;
    end if;
    if C_FSL_EXCEPTION and I >= EDR_TYPE'left and I <= EDR_TYPE'right then
      tmp(idx):= b2std(WB_Sel_SPR_EDR);
      idx     := idx + 1;
    end if;
    if C_PVR /= 0 and I >= PVR_TYPE'left and I <= PVR_TYPE'right then
      tmp(idx):= b2std(WB_Sel_SPR_PVR);
    end if;
    
    -- Group the used select signals.
    for I in tmp'range loop
      tmp2(I / LUT_SIZE)  := tmp2(I / LUT_SIZE) or tmp(I);
    end loop;  
    
    return tmp2;
  end function Map_Used_Select_Bits;
  
    
begin

  ----------------------------------------
  -- FPGA code path
  -- Help to improve the logic depth and
  -- resource utilization by allocating
  -- logic more efficient (than xst).
  ----------------------------------------

  FPGA_Target: if (C_TARGET /= RTL) generate

    signal Data_Bits            : Data_Vector(DATA_TYPE'range);
    signal Select_Bits          : Ctrl_Vector(DATA_TYPE'range);
    signal WB_Exception_Taken_I : std_logic;
    
  begin

    WB_Exception_Taken_I        <= '1' when WB_Exception_Taken else '0';

    ALL_Bits: for I in DATA_TYPE'right downto DATA_TYPE'left generate
    
      signal local_select     : std_logic_vector(0 to (BIT_SIZE(I) - 1) / LUT_SIZE);
      signal local_data       : std_logic_vector(0 to BIT_SIZE(I) - 1);
    
    begin
      
      -- Extract data bits
      Select_Bits(I) <= Map_Used_Select_Bits(I,
                                             WB_Sel_DataBus_Read_Data,
                                             WB_Sel_MEM_Res,
                                             WB_Sel_MUL_Res,
                                             WB_Sel_FPU_Res,
                                             WB_Sel_MMU_Res,
                                             WB_Sel_SPR_ESR,
                                             WB_Sel_SPR_EAR,
                                             WB_Sel_SPR_EDR,
                                             WB_Sel_SPR_FSR,
                                             WB_Sel_SPR_PVR,
                                             WB_Sel_SPR_BTR);
      Data_Bits(I)   <= Map_Used_Data_Bits(I,
                                           WB_Steered_Read_Data,
                                           WB_MEM_Result,
                                           WB_Mul_Result,
                                           WB_FPU_Result,
                                           WB_MMU_Result,
                                           WB_ESR,
                                           WB_EAR,
                                           WB_EDR,
                                           WB_FSR,
                                           WB_PVR,
                                           WB_BTR);

      local_select    <= Select_Bits(I)(0 to (BIT_SIZE(I) - 1) / LUT_SIZE);
      local_data      <= Data_Bits(I)(0 to BIT_SIZE(I) - 1);
    
      Wb_Mux_I1: WB_Mux_Bit
        generic map(
          C_TARGET            => C_TARGET,
          C_LUT_SIZE          => LUT_SIZE,
          C_DATA_WIDTH        => BIT_SIZE(I)
        )
        port map(
          Select_Bits         => local_select,
          Data_Bits           => local_data,
        
          WB_Exception_Taken  => WB_Exception_Taken_I,
          WB_PC               => WB_PC(I),
          
          WB_Fwd              => WB_Fwd(I)
        );
    end generate ALL_Bits;
    
  end generate FPGA_Target;


  ----------------------------------------
  -- RTL code path:
  -- Make the evaluation of WB_Fwd by using 
  -- 'and'-'or' logic and letting xst decide
  -- the implementation
  ----------------------------------------

  RTL_Target: if (C_TARGET = RTL) generate
    
    -- Enable signals for masking.
    signal enable_WB_MEM_Result        : DATA_TYPE;
    signal enable_WB_Steered_Read_Data : DATA_TYPE;
    signal enable_WB_Mul_Result        : DATA_TYPE;
    signal enable_WB_FPU_Result        : DATA_TYPE;
    signal enable_WB_MMU_Result        : DATA_TYPE;
    signal enable_WB_ESR               : DATA_TYPE;
    signal enable_WB_EAR               : DATA_TYPE;
    signal enable_WB_EDR               : DATA_TYPE;
    signal enable_WB_FSR               : DATA_TYPE;
    signal enable_WB_PVR               : DATA_TYPE;
    signal enable_WB_BTR               : DATA_TYPE;
  
    -- Expaned input data signals.
    signal WB_ESR_I                    : DATA_TYPE;
    signal WB_FSR_I                    : DATA_TYPE;
    
    -- Intermediate result signal.
    signal wb_result                   : DATA_TYPE;
    signal WB_Exception_Taken_I        : DATA_TYPE;
    
  begin
    -- Expand selector to fit data width.
    enable_WB_MEM_Result        <= (others => '1') when true               else (others => '0');
    enable_WB_Steered_Read_Data <= (others => '1') when true               else (others => '0');
    enable_WB_Mul_Result        <= (others => '1') when C_USE_HW_MUL       else (others => '0');
    enable_WB_FPU_Result        <= (others => '1') when C_USE_FPU          else (others => '0');
    enable_WB_MMU_Result        <= (others => '1') when C_USE_MMU >= C_MMU_PROTECT
                                                                           else (others => '0');
    enable_WB_FSR               <= (others => '1') when C_USE_FPU          else (others => '0');
    enable_WB_ESR               <= (others => '1') when C_USE_EXCEPTIONS   else (others => '0');
    enable_WB_EAR               <= (others => '1') when C_USE_EXCEPTIONS   else (others => '0');
    enable_WB_EDR               <= (others => '1') when C_USE_EXCEPTIONS   else (others => '0');
    enable_WB_BTR               <= (others => '1') when C_USE_EXCEPTIONS   else (others => '0');
    enable_WB_PVR               <= (others => '1') when C_PVR /= 0         else (others => '0');
    WB_Exception_Taken_I        <= (others => '1') when WB_Exception_Taken else (others => '0');
    
    -- Expand sub vectors to fill data width.
    Expand_WB_Result_In_Data: process(WB_ESR, WB_FSR)
    begin
      WB_ESR_I                    <= (others => '0');
      WB_ESR_I(ESR_REG_POS_TYPE)  <= WB_ESR;
      WB_FSR_I                    <= (others => '0');
      WB_FSR_I(FSR_REG_POS_TYPE)  <= WB_FSR;
    end process Expand_WB_Result_In_Data;
    
    -- Generate result by OR:ing instread of multiplexing.
    wb_result <=  ( WB_MEM_Result         and enable_WB_MEM_Result ) or
                  ( WB_Steered_Read_Data  and enable_WB_Steered_Read_Data ) or
                  ( WB_Mul_Result         and enable_WB_Mul_Result ) or
                  ( WB_FPU_Result         and enable_WB_FPU_Result ) or
                  ( WB_MMU_Result         and enable_WB_MMU_Result ) or
                  ( WB_ESR_I              and enable_WB_ESR ) or
                  ( WB_EAR                and enable_WB_EAR ) or
                  ( WB_EDR                and enable_WB_EDR ) or
                  ( WB_FSR_I              and enable_WB_FSR ) or
                  ( WB_PVR                and enable_WB_PVR ) or
                  ( WB_BTR                and enable_WB_BTR );
    
    -- Add the exception PC as a separate case since it has 
    -- higher priority than the rest that are or:ed together.
    WB_Fwd <= ( (     WB_Exception_Taken_I ) and WB_PC     ) or
              ( ( not WB_Exception_Taken_I ) and wb_result );
  end generate RTL_Target;
 

end architecture IMP;